From nobody Fri Dec 19 17:11:54 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A44923875D; Wed, 2 Apr 2025 11:32:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743593536; cv=none; b=KFJ0xZtAPFzS/02CW2npJdTBE7q9F3wAwddsNnMNNy3XIjrGDgemmo/f5wrD6lNR5owf6wRCjjIGtICBt9jbMKZaGANOBAQboIQ91DLLNNbO6ecInUsRVxhgEKdZUux9C/49SVRuHXQsr5vI25hMGbgnEbxoPU2rO2zK+OqFv8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743593536; c=relaxed/simple; bh=QsKx5DKMzwtV+jd3NDrAZU5u8r9jufWg9hDR5rqYc6g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sKn+PQqMaSv3BoGT/MNStlaVn0t+JT0MmvyiY9zuYc7n32qleYQJ08ZGgr+2044IwHJAM59ijHA5HSvAEBeUDleYeflFes3svv54dF16AeAkkp7xXrwW1UFr0+UQVXkEOHmwO6+g7jsYElGEUA7bHX4dxIkUBF6zQvYUORvrjtg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=tD6I4wXv; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tD6I4wXv" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 532BW9Kv3915804 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 2 Apr 2025 06:32:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743593529; bh=T7GXSrCelE7fze5pqE3ynsiOQxqvgOU5MvzsMaU1iQM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tD6I4wXvD35uwxLxJJtd26v2QWO9g7qPX4fhrz1ED2Su/c4P2atXutcsz1MmKDxRH /YAB9gTU6dcTkpd5PN23qWquMYDUvcaeUxD3caaQnl5HYbWmA2SRHzQ/bGCU9WVS25 c7iPJNFM6OmzQvYOTv6PvaXW0EmUgjLRWDF8pbp4= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 532BW8bf103477 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Apr 2025 06:32:08 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Apr 2025 06:32:08 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Apr 2025 06:32:08 -0500 Received: from localhost (jayesh-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.210]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 532BW755036731; Wed, 2 Apr 2025 06:32:08 -0500 From: Jayesh Choudhary To: , , , , , , , CC: , , , , , Subject: [PATCH v2 3/5] arm64: dts: ti: k3-j7200: Add PCIe ctrl node to scm_conf region Date: Wed, 2 Apr 2025 17:01:59 +0530 Message-ID: <20250402113201.151195-4-j-choudhary@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402113201.151195-1-j-choudhary@ti.com> References: <20250402113201.151195-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Andrew Davis This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe node. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-j7200-evm-pcie1-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso b/arch/arm64= /boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso index 3cc315a0e084..281076d905f3 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-pcie1-ep.dtso @@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 { dma-coherent; phys =3D <&serdes0_pcie_link>; phy-names =3D "pcie-phy"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5ab510a0605f..dbb000657377 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -32,6 +32,11 @@ scm_conf: scm-conf@100000 { #size-cells =3D <1>; ranges =3D <0x00 0x00 0x00100000 0x1c000>; =20 + pcie1_ctrl: pcie-ctrl@4074 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4074 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x4080 0x20>; @@ -764,7 +769,7 @@ pcie1_rc: pcie@2910000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <4>; power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; --=20 2.34.1