From nobody Fri Dec 19 20:22:00 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6FD9238168; Wed, 2 Apr 2025 11:32:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743593546; cv=none; b=k/eWQSju8jjtPOg2mpwuxDZxYs+9Su3AbWs5mhjMmZzsgn0NRTaBs6bcZaa9wpjdc5VbT5971QbDvg7U95Dl9ck+x4B6d7nZI9Fi9u1VhUyWEjb9oGIbXTc+jaPcnbSF6XnlHZgxfHSJ0xoCUd105a46PyfO+3R8WE8CG1viBH0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743593546; c=relaxed/simple; bh=EKiy+DjOCWiRGvapl8jezfSnRx56FINAT9C2suGMVXc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k+OjanX1Dl4gqIisB1AAg9BBNP9rXI/FAGbsxkZoUkfe1laepteVCZ3qKnbjLUQns+fLVIp67+Ola7/NWU1DmLxaZN6h+E1rtCrB99lNwokUHv68fp6A4vWiHbroN7IN7V6IGgX75qlNOfaxRsKNMv0c/Q86euG1zkesDNCjXR8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=THaRjxo8; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="THaRjxo8" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 532BW7jB3385651 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 2 Apr 2025 06:32:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743593527; bh=n+FwtTM6uNx2mwGR3w0xSfj5ZDKKSdhNsKMhEYgi3lo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=THaRjxo89cW0RISge3BpOsUn5LuY1H3XoLFagS9DxNKH49sCu9a6JeI11s5MgGVmA puvvgQhZvchdBeK4f4dkQVwP1Mz4pzNeQ48KuKjuzNDIbOr/srsx/vyO3Tx/jF08pa WGMt07SXzPWYjUNJjjdZwsvNCyzxuxB8l9vgNpWA= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 532BW7tQ013392 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Apr 2025 06:32:07 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Apr 2025 06:32:06 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Apr 2025 06:32:06 -0500 Received: from localhost (jayesh-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.210]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 532BW5wB017398; Wed, 2 Apr 2025 06:32:06 -0500 From: Jayesh Choudhary To: , , , , , , , CC: , , , , , Subject: [PATCH v2 2/5] arm64: dts: ti: k3-j721e: Add PCIe ctrl node to scm_conf region Date: Wed, 2 Apr 2025 17:01:58 +0530 Message-ID: <20250402113201.151195-3-j-choudhary@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250402113201.151195-1-j-choudhary@ti.com> References: <20250402113201.151195-1-j-choudhary@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Andrew Davis This region is used for controlling the function of the PCIe IP. It is compatible with "ti,j784s4-pcie-ctrl", add this here and use it with the PCIe nodes. Signed-off-by: Andrew Davis [j-choudhary@ti.com: Add changes to k3-j721e-evm-pcie1-ep.dtso] Signed-off-by: Jayesh Choudhary Reviewed-by: Siddharth Vadapalli --- .../boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso | 2 +- .../boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 28 ++++++++++++++++--- 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso b/arch/arm64= /boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso index 4062709d6579..a8a502a6207f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso @@ -38,7 +38,7 @@ pcie0_ep: pcie-ep@2900000 { reg-names =3D "intd_cfg", "user_cfg", "reg", "mem"; interrupt-names =3D "link_state"; interrupts =3D ; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <1>; power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso b/arch/arm64= /boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso index a8cccdcf3e3b..436085157a69 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-pcie1-ep.dtso @@ -48,6 +48,6 @@ pcie1_ep: pcie-ep@2910000 { dma-coherent; phys =3D <&serdes1_pcie_link>; phy-names =3D "pcie-phy"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index af3d730154ac..d7263ad43163 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -44,6 +44,26 @@ scm_conf: scm-conf@100000 { #size-cells =3D <1>; ranges =3D <0x0 0x0 0x00100000 0x1c000>; =20 + pcie0_ctrl: pcie-ctrl@4070 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4070 0x4>; + }; + + pcie1_ctrl: pcie-ctrl@4074 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4074 0x4>; + }; + + pcie2_ctrl: pcie-ctrl@4078 { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x4078 0x4>; + }; + + pcie3_ctrl: pcie-ctrl@407c { + compatible =3D "ti,j784s4-pcie-ctrl", "syscon"; + reg =3D <0x407c 0x4>; + }; + serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; reg =3D <0x4080 0x50>; @@ -946,7 +966,7 @@ pcie0_rc: pcie@2900000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4070>; + ti,syscon-pcie-ctrl =3D <&pcie0_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; @@ -975,7 +995,7 @@ pcie1_rc: pcie@2910000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4074>; + ti,syscon-pcie-ctrl =3D <&pcie1_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; @@ -1004,7 +1024,7 @@ pcie2_rc: pcie@2920000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x4078>; + ti,syscon-pcie-ctrl =3D <&pcie2_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; @@ -1033,7 +1053,7 @@ pcie3_rc: pcie@2930000 { interrupt-names =3D "link_state"; interrupts =3D ; device_type =3D "pci"; - ti,syscon-pcie-ctrl =3D <&scm_conf 0x407c>; + ti,syscon-pcie-ctrl =3D <&pcie3_ctrl 0x0>; max-link-speed =3D <3>; num-lanes =3D <2>; power-domains =3D <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; --=20 2.34.1