From nobody Mon Feb 9 07:25:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E93A1E8837; Wed, 2 Apr 2025 09:25:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743585930; cv=none; b=o+k/Ow6huXc2tEa+RoRWV8f00Fg6UhGypkUkdh5PvhEpM+bYZXiwqzJJQf4ROZiXrkCrpytnw0ctQ7rxBZolvU7XARRcfDHVHvquYmOyEv3bXZd39bjF6hQC82TWwMK1C6GgtlJdCE7TTiqsn4nIfkrN4y2jpXPGTg67GO9C+Tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743585930; c=relaxed/simple; bh=y90OORQmQst754NgohihyeKjzbwkvGiSh/5wkUbDPBQ=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=LNBsezSgps+fSDGAV7cub/Q81Vc/vwqAN53iuapnLW7sREujsGRnx71rMlz4c/O1nNzPMjElFBUOqeXCPFokuIjy9jGAMUqh3V/60HoKVrwpQj9a6no8BkOwMZxT3iaDXw8dcKf4hcOn3aheidUe5iOCnbzhfbPDItsazJRViPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 051CEC4CEDD; Wed, 2 Apr 2025 09:25:27 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen , stable@vger.kernel.org, Yinbo Zhu Subject: [PATCH] irqchip/loongson-liointc: Support to set IRQ_TYPE_EDGE_BOTH Date: Wed, 2 Apr 2025 17:25:00 +0800 Message-ID: <20250402092500.514305-1-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some peripheral subsystems request IRQ_TYPE_EDGE_BOTH interrupt type and report request failures on LIOINTC. To avoid such failures we support to set IRQ_TYPE_EDGE_BOTH type on LIOINTC, by setting LIOINTC_REG_INTC_EDGE to true and keep LIOINTC_REG_INTC_POL as is. Cc: stable@vger.kernel.org Signed-off-by: Yinbo Zhu Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-liointc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index 2b1bd4a96665..c0c8ef8d27cf 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -128,6 +128,10 @@ static int liointc_set_type(struct irq_data *data, uns= igned int type) liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false); liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true); break; + case IRQ_TYPE_EDGE_BOTH: + liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); + /* Requester need "both", keep LIOINTC_REG_INTC_POL as is */ + break; case IRQ_TYPE_EDGE_RISING: liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true); liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false); --=20 2.47.1