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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43eb613aabesm14292515e9.39.2025.04.02.02.10.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Apr 2025 02:10:19 -0700 (PDT) From: Andrew Cooper To: LKML Cc: Andrew Cooper , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Subject: x86/idle: Remove barriers for X86_BUG_CLFLUSH_MONITOR Date: Wed, 2 Apr 2025 10:10:17 +0100 Message-Id: <20250402091017.1249019-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 7e98b7192046 ("x86, idle: Use static_cpu_has() for CLFLUSH workaround, add barriers") adds barriers, justified with: ... and add memory barriers around it since the documentation is explicit that CLFLUSH is only ordered with respect to MFENCE. The SDM currently states: Executions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes, locked read-modify-write instructions, and fence instructions[1]. With footnote 1 reading: Earlier versions of this manual specified that executions of the CLFLUSH instruction were ordered only by the MFENCE instruction. All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above. i.e. The SDM was incorrect at the time, and barriers should not have been inserted. Double checking the original AAI65 errata (not available from intel.com any more) shows no mention of barriers either. Additionally, drop the static_cpu_has_bug() and use a plain alternative. The workaround is a single instruction, with identical address setup to the MONITOR instruction. Link: https://web.archive.org/web/20090219054841/http://download.intel.com/= design/xeon/specupdt/32033601.pdf Fixes: 7e98b7192046 ("x86, idle: Use static_cpu_has() for CLFLUSH workaroun= d, add barriers") Signed-off-by: Andrew Cooper Acked-by: Borislav Petkov (AMD) --- CC: Thomas Gleixner CC: Ingo Molnar CC: Borislav Petkov CC: Dave Hansen CC: x86@kernel.org CC: "H. Peter Anvin" CC: linux-kernel@vger.kernel.org diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h index ce857ef54cf1..dff9e7d854ed 100644 --- a/arch/x86/include/asm/mwait.h +++ b/arch/x86/include/asm/mwait.h @@ -116,13 +116,11 @@ static __always_inline void __sti_mwait(unsigned long= eax, unsigned long ecx) static __always_inline void mwait_idle_with_hints(unsigned long eax, unsig= ned long ecx) { if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test(= )) { - if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) { - mb(); - clflush((void *)¤t_thread_info()->flags); - mb(); - } + const void *addr =3D ¤t_thread_info()->flags; =20 - __monitor((void *)¤t_thread_info()->flags, 0, 0); + alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, + [addr] "a" (addr)); + __monitor(addr, 0, 0); =20 if (!need_resched()) { if (ecx & 1) {