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Wed, 02 Apr 2025 08:17:41 -0700 (PDT) From: Peter Griffin Date: Wed, 02 Apr 2025 16:17:32 +0100 Subject: [PATCH v6 3/4] pinctrl: samsung: add gs101 specific eint suspend/resume callbacks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250402-pinctrl-fltcon-suspend-v6-3-78ce0d4eb30c@linaro.org> References: <20250402-pinctrl-fltcon-suspend-v6-0-78ce0d4eb30c@linaro.org> In-Reply-To: <20250402-pinctrl-fltcon-suspend-v6-0-78ce0d4eb30c@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, kernel-team@android.com, jaewon02.kim@samsung.com, Peter Griffin , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA gs101 differs to other SoCs in that fltcon1 register doesn't always exist. Additionally the offset of fltcon0 is not fixed and needs to use the newly added eint_fltcon_offset variable. Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration= ") Cc: stable@vger.kernel.org # depends on the previous three patches Reviewed-by: Andr=C3=A9 Draszik Signed-off-by: Peter Griffin --- Changes since v2: * make it clear exynos_set_wakeup(bank) is conditional on bank type (Andre) * align style where the '+' is placed (Andre) * remove unnecessary braces (Andre) --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 24 ++++----- drivers/pinctrl/samsung/pinctrl-exynos.c | 71 ++++++++++++++++++++++= ++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 2 + 3 files changed, 85 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index 4b5d4e436a337ff13dee6ef740a1500eaf86cc12..9fd894729a7b87c3e144ff90921= a1cadbde93d3d 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1762,15 +1762,15 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl= [] __initconst =3D { .pin_banks =3D gs101_pin_alive, .nr_banks =3D ARRAY_SIZE(gs101_pin_alive), .eint_wkup_init =3D exynos_eint_wkup_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (FAR_ALIVE) */ .pin_banks =3D gs101_pin_far_alive, .nr_banks =3D ARRAY_SIZE(gs101_pin_far_alive), .eint_wkup_init =3D exynos_eint_wkup_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (GSACORE) */ .pin_banks =3D gs101_pin_gsacore, @@ -1784,29 +1784,29 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl= [] __initconst =3D { .pin_banks =3D gs101_pin_peric0, .nr_banks =3D ARRAY_SIZE(gs101_pin_peric0), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (PERIC1) */ .pin_banks =3D gs101_pin_peric1, .nr_banks =3D ARRAY_SIZE(gs101_pin_peric1), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI1) */ .pin_banks =3D gs101_pin_hsi1, .nr_banks =3D ARRAY_SIZE(gs101_pin_hsi1), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI2) */ .pin_banks =3D gs101_pin_hsi2, .nr_banks =3D ARRAY_SIZE(gs101_pin_hsi2), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, }; =20 diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/sam= sung/pinctrl-exynos.c index 18c327f7e313355c4aba72f49a79b1697244f1ba..0879684338c772e484174a94ac2= c274cc7d932ed 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -800,6 +800,41 @@ void exynos_pinctrl_suspend(struct samsung_pin_bank *b= ank) } } =20 +void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save =3D bank->soc_priv; + const void __iomem *regs =3D bank->eint_base; + + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + save->eint_con =3D readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + + save->eint_fltcon0 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset); + + /* fltcon1 register only exists for pins 4-7 */ + if (bank->nr_pins > 4) + save->eint_fltcon1 =3D readl(regs + + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset + 4); + + save->eint_mask =3D readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", + bank->name, save->eint_fltcon0); + if (bank->nr_pins > 4) + pr_debug("%s: save fltcon1 %#010x\n", + bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) { + exynos_set_wakeup(bank); + } +} + void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; @@ -819,6 +854,42 @@ void exynosautov920_pinctrl_suspend(struct samsung_pin= _bank *bank) } } =20 +void gs101_pinctrl_resume(struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save =3D bank->soc_priv; + + void __iomem *regs =3D bank->eint_base; + void __iomem *eint_fltcfg0 =3D regs + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset; + + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + + pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, + readl(eint_fltcfg0), save->eint_fltcon0); + + /* fltcon1 register only exists for pins 4-7 */ + if (bank->nr_pins > 4) + pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, + readl(eint_fltcfg0 + 4), save->eint_fltcon1); + + pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, eint_fltcfg0); + + if (bank->nr_pins > 4) + writel(save->eint_fltcon1, eint_fltcfg0 + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); + } +} + void exynos_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index 3a771862b4b1762b32f9e067b011e80cfebb99d2..2bee52b61b9317ff79c618c1dc5= 3e98242805087 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -244,6 +244,8 @@ void exynosautov920_pinctrl_resume(struct samsung_pin_b= ank *bank); void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); void exynos_pinctrl_resume(struct samsung_pin_bank *bank); +void gs101_pinctrl_suspend(struct samsung_pin_bank *bank); +void gs101_pinctrl_resume(struct samsung_pin_bank *bank); struct samsung_retention_ctrl * exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, const struct samsung_retention_data *data); --=20 2.49.0.504.g3bcea36a83-goog