From nobody Fri May 9 12:43:02 2025
Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com
[209.85.214.201])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id E834720D502
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:15 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.214.201
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525797; cv=none;
b=pK3YRFu1qHUupc8IioiybcWNwK3z0MMNvneuVU4Ax4GEqMTn76AhYiCbB6fl/w4fWAGeZG9bvWP3EHeplrrsPOufCK5VZtA+TncGwQCxrpYpu0vcKMPBQd4Bwivltk7azWcPlcu7qHJtb1G0DNl9Mks0Q32ISi0EUSSbrfT28eA=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525797; c=relaxed/simple;
bh=IX2hIEFDZxr1s7mPt549rL+2MP5J40qc7gWfaob7z2I=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=SIeDx+HmqCNe6jOQXA8WeXRXbDEltBULpKqRM6l2Y+Ode6SBrJ3KW11bKxHQzNFrWZIErYWP3PTdvd3grl/XRfTbmHuKD7waaikz8ZyXUH810bXCs/1ZuHnl95t82bE934OVZRssdVPQ+lTw/xhjFITj2oMTPHwh3Br667dBsas=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=2RV4GpZl; arc=none smtp.client-ip=209.85.214.201
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="2RV4GpZl"
Received: by mail-pl1-f201.google.com with SMTP id
d9443c01a7336-22651aca434so108953515ad.1
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:15 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525795; x=1744130595;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=tjqTIWn86XObYZ0dlBWL1fKISTH8kVDuFqpN5liSeqY=;
b=2RV4GpZlnot4SCQ5wABLNoj1h5/geg50gJV/aZ0WrLzGYB/VV3xhNfojzwmHO0uDYz
g31k7XvWqBamA1iirpWdFwlIerGnukt8vXTN16dbap04aiQd38ioMrYWgU3kFFc5odti
G3p58wvcGb0TWKOKcZh4W9l5+3syRSR1wYrrRMdvuji2Yn4VG1pIqMWInZnmw4M6Sezs
7l2ZkZNNoe0TUoaH4AB6Ite60SMnnBmvXQgUhl2So3HEUiHXZv9jlhMmxdb3We6fpkHa
8wqwkYjn53FsRSZfxI7C7rZRuTeCyd7KO4GJrlszzn9sFKa8uVGmvZKcdJaFMIDs46Ln
Ejhg==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525795; x=1744130595;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=tjqTIWn86XObYZ0dlBWL1fKISTH8kVDuFqpN5liSeqY=;
b=Ki/PHwKPXGBCrTToVzPBjQFsrOvRNPYJ0ouacuhs0Ph5x8dgBGAluNCaTeNdfRg1sJ
RK3sY0Vo9+a2AV+wL3e2Bd4LpCx95rnwoFhLFHkqnuweFUUj/vzYf/Maxdoy1Z2snZNV
Dql4TnUvR0tyMZ/+x2K9iUqFoBuDOoiABH7V4sGtbURWrQgGgQRwxnq7xLepAOUWOf/+
cRJGs2kL+I/DG9y7f2i9+P8I2c3s114LauMRD0fy0m3neQUgrTBEGswnDmdYw6Pu3GXh
Ve8xfr9nJ4TLXPVZpC7aPKhpYRteDPpTfePZzIOdAqVBRRH3UdwAkgeJZjn1gt7lVVX8
4RpA==
X-Gm-Message-State: AOJu0YzRGyrbvkTfoKWSOSk9ZBX/8PyarjfWaeL9JNsumask1ZbvAY6E
EBqLDWn+lsmNT00x7mDlPZbEseboX3vMjZEBj3Tx21pBA3g2L0joYqmewTJl3lCvzA64OvGHQZl
kJA==
X-Google-Smtp-Source:
AGHT+IF7k6V4hI9NSmqeQR7Ldpinq9z+9LeYTtWSOW3n7weH2d7MasMbpC1/xTtwiRZrQxL5X02TqjREFfU=
X-Received: from pfbhw8.prod.google.com
([2002:a05:6a00:8908:b0:730:7e2d:df69])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a05:6a00:1309:b0:736:450c:fa54
with SMTP id d2e1a72fcca58-7398036acbemr20074041b3a.6.1743525795261; Tue, 01
Apr 2025 09:43:15 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:40 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-2-seanjc@google.com>
Subject: [PATCH v2 1/8] x86/irq: Ensure initial PIR loads are performed
exactly once
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Ensure the PIR is read exactly once at the start of handle_pending_pir(),
to guarantee that checking for an outstanding posted interrupt in a given
chuck doesn't reload the chunk from the "real" PIR. Functionally, a reload
is benign, but it would defeat the purpose of pre-loading into a copy.
Fixes: 1b03d82ba15e ("x86/irq: Install posted MSI notification handler")
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kernel/irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index feca4f20b06a..85fa2db38dc4 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -414,7 +414,7 @@ static __always_inline bool handle_pending_pir(u64 *pir=
, struct pt_regs *regs)
bool handled =3D false;
=20
for (i =3D 0; i < 4; i++)
- pir_copy[i] =3D pir[i];
+ pir_copy[i] =3D READ_ONCE(pir[i]);
=20
for (i =3D 0; i < 4; i++) {
if (!pir_copy[i])
--=20
2.49.0.472.ge94155a9ec-goog
From nobody Fri May 9 12:43:02 2025
Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com
[209.85.214.201])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id B234120E313
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:17 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.214.201
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525799; cv=none;
b=fo+WYRLk04yX2XDMG1bQaMMVQKgan4GQxNWYLonNrWwLmYizqGZQhZ23J0vJwvfUViL7L6b5+1C/XVRQ1SRm6FLGZfKK9c6cmHDTKgQ6u/AbYrmAs2p9sjUo+oQBcx2SVBRgjq8AcuTI9Z0E3cacpnnusUrAkHAjaPWwtxkgqn4=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525799; c=relaxed/simple;
bh=jGuwQyi4PUoNb9tVJY2auvrWnk5ldsHm2gyBlrKR40I=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=Gp63UGaJ5MwwJk1P76eI9tnLsJjDSqX5EMs06LfZrhBnRc1IrSYWeX4y0jezzPYn3+anHNRAE/pA21qVe27q1Ws8B5E/0Zp72Ttvj3TUkE30+BPC1i7XBLiY7EgF+H/PPUTsTar8g6FpZDanPyLqBfV7EhR6NPsN5iI9+LhXhBo=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=hVa7N9El; arc=none smtp.client-ip=209.85.214.201
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="hVa7N9El"
Received: by mail-pl1-f201.google.com with SMTP id
d9443c01a7336-225505d1ca5so98744795ad.2
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:17 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525797; x=1744130597;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=cDvP5BZpEDyKBmPstvDIZN80Syur3P8OaOWHbakcInk=;
b=hVa7N9ElrbNfcAg1jLOLP5EPxthvxMGVYFreS7KIRdo6rOKEzm52+yLMNQleULnE4g
MiJm9t67idfdGe0PgNVfr/uVIZg4AWNy9IWk7aAVquEypW1Jx6ZonnVmYiNGtutctN/g
op7VCaUpr3vLPtm0tnN3wMDWeBh2fMqjkC8V+n5cITDfoWrfTnTBWqhk87x8hzRaJvX9
k6dpgkiJ0Q2Hie7qI9zcEl856CIUem2YIUqC49m5hdknnNoWXTxR2IkTZ7TyzJhJmG8w
3XTdpIsuMe8McNsA1BAaWAW4yxcQOPY/RGyMZI6NmX3XAiFcczj/K7PtJJJk0rAPEu8k
6uaw==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525797; x=1744130597;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=cDvP5BZpEDyKBmPstvDIZN80Syur3P8OaOWHbakcInk=;
b=DpqVFFMqxDJKDuI40ntd6bUor4jmsaRibUO0PwXzL9Bc02zBX91qSwwss8UVCdk/ZW
pPwUcu6iX+KBXEeTAKHbA3cPnsn0oXQos5GmdMIJNN9QQRzbrFdnFkPju++Y6cBQdsyL
nelSLPDxKA7SPBrEahm/gHd3tG2E/m80BNEcfoCDumxboB0GUmXciZyexdqZ5uO3SQlr
yj3/M3+SM5LV6PZzOcdQT2ZHbneD/LP8oaGGk9EsgF6jZzFXL+NkYHmttVtAcs/PTjkQ
MQj6BXA7Go+J0kMbf4lV5bVV2x/8pAFZa/bnALlz8Ir3WFxdBO6lGzWGsacXjeAp/UZI
d3xQ==
X-Gm-Message-State: AOJu0Yyyf9sTEnJv4KDFXSnkYkDR+FDwkY5IdLzy4s+FHTmCZDVYhixH
i5O59MF12crHXLnEsvN9AHnvl10UMmIi9bEj3YniIcbJP9ySfaqQdwuVjB2MM1YU4C11P7iYYwG
XOQ==
X-Google-Smtp-Source:
AGHT+IGxxWnUBIlHU15BzVG9W/GeQ6sCwXTyMrI61xhzsb0eCK4R7c40Z6JqSwtcB6fShFN5RLpLo6Zov7E=
X-Received: from pfbfo6.prod.google.com
([2002:a05:6a00:6006:b0:736:3cd5:ba36])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a05:6a00:1901:b0:739:48f2:4374
with SMTP id d2e1a72fcca58-739b5ff7f6cmr5338777b3a.10.1743525797032; Tue, 01
Apr 2025 09:43:17 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:41 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-3-seanjc@google.com>
Subject: [PATCH v2 2/8] x86/irq: Track if IRQ was found in PIR during initial
loop (to load PIR vals)
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Track whether or not at least one IRQ was found in PIR during the initial
loop to load PIR chunks from memory. Doing so generates slightly better
code (arguably) for processing the for-loop of XCHGs, especially for the
case where there are no pending IRQs.
Note, while PIR can be modified between the initial load and the XCHG, it
can only _gain_ new IRQs, i.e. there is no danger of a false positive due
to the final version of pir_copy[] being empty.
Opportunistically convert the boolean to an "unsigned long" and compute
the effective boolean result via bitwise-OR. Some compilers, e.g.
clang-14, need the extra "hint" to elide conditional branches.
Opportunistically rename the variable in anticipation of moving the PIR
accesses to a common helper that can be shared by posted MSIs and KVM.
Old:
<+74>: test %rdx,%rdx
<+77>: je 0xffffffff812bbeb0 <handle_pending_pir+144>
<pir[0]>
<+88>: mov $0x1,%dl>
<+90>: test %rsi,%rsi
<+93>: je 0xffffffff812bbe8c <handle_pending_pir+108>
<pir[1]>
<+106>: mov $0x1,%dl
<+108>: test %rcx,%rcx
<+111>: je 0xffffffff812bbe9e <handle_pending_pir+126>
<pir[2]>
<+124>: mov $0x1,%dl
<+126>: test %rax,%rax
<+129>: je 0xffffffff812bbeb9 <handle_pending_pir+153>
<pir[3]>
<+142>: jmp 0xffffffff812bbec1 <handle_pending_pir+161>
<+144>: xor %edx,%edx
<+146>: test %rsi,%rsi
<+149>: jne 0xffffffff812bbe7f <handle_pending_pir+95>
<+151>: jmp 0xffffffff812bbe8c <handle_pending_pir+108>
<+153>: test %dl,%dl
<+155>: je 0xffffffff812bbf8e <handle_pending_pir+366>
New:
<+74>: mov %rax,%r8
<+77>: or %rcx,%r8
<+80>: or %rdx,%r8
<+83>: or %rsi,%r8
<+86>: setne %bl
<+89>: je 0xffffffff812bbf88 <handle_pending_pir+360>
<+95>: test %rsi,%rsi
<+98>: je 0xffffffff812bbe8d <handle_pending_pir+109>
<pir[0]>
<+109>: test %rdx,%rdx
<+112>: je 0xffffffff812bbe9d <handle_pending_pir+125>
<pir[1]>
<+125>: test %rcx,%rcx
<+128>: je 0xffffffff812bbead <handle_pending_pir+141>
<pir[2]>
<+141>: test %rax,%rax
<+144>: je 0xffffffff812bbebd <handle_pending_pir+157>
<pir[3]>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kernel/irq.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 85fa2db38dc4..5d732ff357ef 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -409,27 +409,28 @@ void intel_posted_msi_init(void)
*/
static __always_inline bool handle_pending_pir(u64 *pir, struct pt_regs *r=
egs)
{
+ unsigned long pir_copy[4], pending =3D 0;
int i, vec =3D FIRST_EXTERNAL_VECTOR;
- unsigned long pir_copy[4];
- bool handled =3D false;
=20
- for (i =3D 0; i < 4; i++)
+ for (i =3D 0; i < 4; i++) {
pir_copy[i] =3D READ_ONCE(pir[i]);
+ pending |=3D pir_copy[i];
+ }
+
+ if (!pending)
+ return false;
=20
for (i =3D 0; i < 4; i++) {
if (!pir_copy[i])
continue;
=20
pir_copy[i] =3D arch_xchg(&pir[i], 0);
- handled =3D true;
}
=20
- if (handled) {
- for_each_set_bit_from(vec, pir_copy, FIRST_SYSTEM_VECTOR)
- call_irq_handler(vec, regs);
- }
+ for_each_set_bit_from(vec, pir_copy, FIRST_SYSTEM_VECTOR)
+ call_irq_handler(vec, regs);
=20
- return handled;
+ return true;
}
=20
/*
--=20
2.49.0.472.ge94155a9ec-goog
From nobody Fri May 9 12:43:02 2025
Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com
[209.85.214.202])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F77620E70F
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:19 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.214.202
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525800; cv=none;
b=coe4p1Wnq1+2j8EWrNi8780MkMDZFs25eFDEGeqNqBvPnxM4TQWcKod3uaTj/cMQP47RiWjxun+wSePu1DVL1ZvZNQNaM16SrdU01C0dfRJES5yj3UUjactQABZsc/3jzRiTpMizXV1t6GXIW2wwmF7qJyySXC7C/WJnw4ca5sg=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525800; c=relaxed/simple;
bh=68XUd7R1fyxPr0p6LhY6RzrECfMFspwxL2oY+XxMEXg=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=ir48YSfUqEgprWTwVpvy7/lcktLIi476a3lRad8evuvoq9auiHg2Bw2XnOmzMT/Cx5mfhK7TB+oEHhKerQRmSTAVHuQ2bIW+gw6f0CKxgYnhH2vg/UFd1yRzjW2iYxKLbveYf5TWojNro29HtBbu22m1smkXuswd1udKyiZbdb4=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=ZH2UDmrz; arc=none smtp.client-ip=209.85.214.202
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="ZH2UDmrz"
Received: by mail-pl1-f202.google.com with SMTP id
d9443c01a7336-224192ff68bso102886535ad.1
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:19 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525798; x=1744130598;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=ENuRHHo4buatmc9xHBzqgn6lL1J28WBga1j/Fc+SdOU=;
b=ZH2UDmrzbMQf54X1EPb1PIhVhq7QjX9j30cxbbKKBoYgjT3m9bpKdxgW8a3AvgscWh
4Y1kU9srYsDeG9r6liy5vdg/d77sqtIEp5B7YYp+/Qy14Uf3BltnAeWLff4Nm7UNONTc
waTVJbAAOYDoas/+1gq3bG9vbqTA0ssszB5cquZ3DiMqYL+2KhowO0+3mquGJ4qIJwSR
fErMn8oN5+HqOaelo59cGP3RmVEGiqkCgJ9/e1wvEX9S8OwoHncU4kp5Dr/x2sv+97PS
9XelIYgW8+PK3+qN6snYIhh7Re3IeAbMVoahGfxn7ID9yO8AOFGxTY0A05Ddi9BUAqyg
q5vA==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525798; x=1744130598;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=ENuRHHo4buatmc9xHBzqgn6lL1J28WBga1j/Fc+SdOU=;
b=fZD8OFLkD+0O77/WlEWHiMvPEtnw02SCYiCgoHBsw5UWSO3TspRtvkPFoYIfgnadcP
8YkvOITXl2r6JOfFmOVFg35kmfgDROY/XPOrhHIbyQjpsq6NqpPDmYzG+E7pGmdz0L03
o70S8oimnHiSu8rBJIqdSGQeJHBncFUimB9mvidDt9CKbGFNoDBhhr2ZIP3l2N5tsfiV
QBZZulUbKakPbXpeXPzFx+fVzK5hriwB+yHXMFsgmazM55mDhV+pNA1kqHOj09L0m+Pe
t9cjlwj4S7OfWF29S7yKp1DkzFTbPb1IsnBoFLUDHbO9eozwlzezvbx76hl7VUMdbO3M
SU3w==
X-Gm-Message-State: AOJu0YwWi9WXlZwzu2CHZEAsomAHmF3tlsDeR8CfFpHcNOVn0P2Aax+1
HfRS3wMEGITKKOH+umuOjeLdU14DWGikt4LqigYfaFQxttwufEsb0ff9jCjvyo7/5cFGqFGNeVu
uxQ==
X-Google-Smtp-Source:
AGHT+IG7uPldPi4KrDzTQHRm25erUUAd10L5t443gFis5z6W+qmvlaB54rM8wSKwHj0ezPMBh17NInSp4ik=
X-Received: from plbm1.prod.google.com ([2002:a17:902:d181:b0:223:2747:3d22])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a17:903:1c7:b0:224:78e:4ebe
with SMTP id d9443c01a7336-2292f9e62cbmr194250575ad.33.1743525798682; Tue, 01
Apr 2025 09:43:18 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:42 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-4-seanjc@google.com>
Subject: [PATCH v2 3/8] KVM: VMX: Ensure vIRR isn't reloaded at odd times when
sync'ing PIR
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Read each vIRR exactly once when shuffling IRQs from the PIR to the vAPIC
to ensure getting the highest priority IRQ from the chunk doesn't reload
from the vIRR. In practice, a reload is functionally benign as vcpu->mutex
is held and so IRQs can be consumed, i.e. new IRQs can appear, but existing
IRQs can't disappear.
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/lapic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 9dbc0f5d9865..cb4aeab914eb 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -667,7 +667,7 @@ bool __kvm_apic_update_irr(u32 *pir, void *regs, int *m=
ax_irr)
for (i =3D vec =3D 0; i <=3D 7; i++, vec +=3D 32) {
u32 *p_irr =3D (u32 *)(regs + APIC_IRR + i * 0x10);
=20
- irr_val =3D *p_irr;
+ irr_val =3D READ_ONCE(*p_irr);
pir_val =3D READ_ONCE(pir[i]);
=20
if (pir_val) {
--=20
2.49.0.472.ge94155a9ec-goog
From nobody Fri May 9 12:43:02 2025
Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com
[209.85.214.201])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C46820FAB9
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:20 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.214.201
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525802; cv=none;
b=aw3XqLTud9TlEwIsR+IP1oFd4yflmeHrMmUhJ3Z5de/zF60l+5gyGCbrItPauCFVxRAC+f3Teabm087J0JzNcF9tia+/K8A1+12GTMR/pCrmavfGXgE2kGOm59zDq68oAtM3X4luX5mvUT2xGKrHW1pxzxr8CY9NPW1nZ+R1YCw=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525802; c=relaxed/simple;
bh=/GjbkA6Kd7hsHZq/P/3sF3zT4FudF94Hv2Bxy1AVK8U=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=ATt4WbkohnM1/L8SA/fq5JcStIroDvZVrwRkBUUdBBjxgL9QZPFdnP4NcFo+EWtJifYoctyz4kMiAK7v6QtBlETldk+5EcYEBD2x42QxBvzdYP6C+NyqROMvMUeadX1QdPBtwcqYNqw4lVTLuBGM0lZNselsoqYNy2iX2kAjTok=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=XDct9ytc; arc=none smtp.client-ip=209.85.214.201
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="XDct9ytc"
Received: by mail-pl1-f201.google.com with SMTP id
d9443c01a7336-224191d9228so5985605ad.3
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:20 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525800; x=1744130600;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=Zwrym7xxEAtgq4x4qvWpfuf9S76CNXdDvpgAdSnAM4Y=;
b=XDct9ytcdGerG8zJTTQxiKoEpO8dmphUu3EL8CFqbq15SUkZCDb8YTza4FcCi5VICZ
PfM7nJn7bHWVkj4NPA4WxIQ5Dqwoejd2H1q6gAjs0O4iqOF7uHWeSu5gH68xII52PX9t
MMNz1U/R4VSgAt2mDP2vOEuwDN3A1/IMnP+cq8wfAc5JxHqbh9Ttm2CVks7J3Ge92+o3
Ly/R5mjckJCXdqS2GBi/D+7nMfrUf8F201xsK7Ladn/UMb4MByif9r5TMnx90cx4wBUt
5Uu1qWYirvbdNLjJdx4mnesAOxIZ2N4BBEDWnzj1NFGi8kr+zJxEs24nuh1MJWlGz/56
NLkg==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525800; x=1744130600;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=Zwrym7xxEAtgq4x4qvWpfuf9S76CNXdDvpgAdSnAM4Y=;
b=IgSO6IxfELcZkwC7N5DyEFVkcKGj3OJrRE+oB/Tpfid06WaW/DfTnci8n8RLmuHO5J
nEb052e5asci2YqId+w4VJTpth3seoOk+mJU7KiyhPYQJ8OqIv03p+gDaDzUW9NrZcXI
kQqfqttbvr6Whqn4S9pn5QA4Po3TXAOXM5V9jRiZjeVDDIkpbTxUkrM8b6wOnjxyNcrK
l3vxQpkBatIhqPp6/1QtfE/KI7qQ6DQHPu7aUoCq7gWbJByYkmL0hWlaQKNWSPAEritm
l3eQigBPEoyvvF7GgtVaHG7KvQgrT53ukvU0E0MMyyF57yy+Zzewtj9cRecQVh4e7/ei
dysQ==
X-Gm-Message-State: AOJu0Yz6kP8cO2g2qMVNSp1geGAUNYQTBmqxNyspC42kP0vUv0C3Sjcs
N8rDbpHFa7VytiEmy+31GshgzgMUCZF/U+RJxIvwOqal529UNmu6/f0nGDvO4w78KNZVoyiDT/t
jwg==
X-Google-Smtp-Source:
AGHT+IFbVo2sDfRTB5QdrlauwzOsHEHDj5i2PQ/L+ccHkR2b9gPNztMxgVK194+kKMnHLMvn4E7liI+Holc=
X-Received: from pfbln19.prod.google.com
([2002:a05:6a00:3cd3:b0:736:a1eb:1520])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a17:902:e74e:b0:220:f59b:6e6
with SMTP id d9443c01a7336-2292f9494e1mr156226415ad.8.1743525800423; Tue, 01
Apr 2025 09:43:20 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:43 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-5-seanjc@google.com>
Subject: [PATCH v2 4/8] x86/irq: KVM: Track PIR bitmap as an "unsigned long"
array
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Track the PIR bitmap in posted interrupt descriptor structures as an array
of unsigned longs instead of using unionized arrays for KVM (u32s) versus
IRQ management (u64s). In practice, because the non-KVM usage is (sanely)
restricted to 64-bit kernels, all existing usage of the u64 variant is
already working with unsigned longs.
Using "unsigned long" for the array will allow reworking KVM's processing
of the bitmap to read/write in 64-bit chunks on 64-bit kernels, i.e. will
allow optimizing KVM by reducing the number of atomic accesses to PIR.
Opportunstically replace the open coded literals in the posted MSIs code
with the appropriate macro. Deliberately don't use ARRAY_SIZE() in the
for-loops, even though it would be cleaner from a certain perspective, in
anticipation of decoupling the processing from the array declaration.
No functional change intended.
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/include/asm/posted_intr.h | 14 +++++++-------
arch/x86/kernel/irq.c | 12 ++++++------
arch/x86/kvm/lapic.c | 9 +++++----
arch/x86/kvm/lapic.h | 4 ++--
arch/x86/kvm/vmx/posted_intr.h | 2 +-
5 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/x86/include/asm/posted_intr.h b/arch/x86/include/asm/post=
ed_intr.h
index de788b400fba..c3e6e4221a5b 100644
--- a/arch/x86/include/asm/posted_intr.h
+++ b/arch/x86/include/asm/posted_intr.h
@@ -8,12 +8,12 @@
=20
#define PID_TABLE_ENTRY_VALID 1
=20
+#define NR_PIR_VECTORS 256
+#define NR_PIR_WORDS (NR_PIR_VECTORS / BITS_PER_LONG)
+
/* Posted-Interrupt Descriptor */
struct pi_desc {
- union {
- u32 pir[8]; /* Posted interrupt requested */
- u64 pir64[4];
- };
+ unsigned long pir[NR_PIR_WORDS]; /* Posted interrupt requested */
union {
struct {
u16 notifications; /* Suppress and outstanding bits */
@@ -43,12 +43,12 @@ static inline bool pi_test_and_clear_sn(struct pi_desc =
*pi_desc)
=20
static inline bool pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
{
- return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
+ return test_and_set_bit(vector, pi_desc->pir);
}
=20
static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
{
- return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS);
+ return bitmap_empty(pi_desc->pir, NR_VECTORS);
}
=20
static inline void pi_set_sn(struct pi_desc *pi_desc)
@@ -105,7 +105,7 @@ static inline bool pi_pending_this_cpu(unsigned int vec=
tor)
if (WARN_ON_ONCE(vector > NR_VECTORS || vector < FIRST_EXTERNAL_VECTOR))
return false;
=20
- return test_bit(vector, (unsigned long *)pid->pir);
+ return test_bit(vector, pid->pir);
}
=20
extern void intel_posted_msi_init(void);
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 5d732ff357ef..3753a8acd009 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -407,12 +407,12 @@ void intel_posted_msi_init(void)
* instead of:
* read, xchg, read, xchg, read, xchg, read, xchg
*/
-static __always_inline bool handle_pending_pir(u64 *pir, struct pt_regs *r=
egs)
+static __always_inline bool handle_pending_pir(unsigned long *pir, struct =
pt_regs *regs)
{
- unsigned long pir_copy[4], pending =3D 0;
+ unsigned long pir_copy[NR_PIR_WORDS], pending =3D 0;
int i, vec =3D FIRST_EXTERNAL_VECTOR;
=20
- for (i =3D 0; i < 4; i++) {
+ for (i =3D 0; i < NR_PIR_WORDS; i++) {
pir_copy[i] =3D READ_ONCE(pir[i]);
pending |=3D pir_copy[i];
}
@@ -420,7 +420,7 @@ static __always_inline bool handle_pending_pir(u64 *pir=
, struct pt_regs *regs)
if (!pending)
return false;
=20
- for (i =3D 0; i < 4; i++) {
+ for (i =3D 0; i < NR_PIR_WORDS; i++) {
if (!pir_copy[i])
continue;
=20
@@ -460,7 +460,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification)
* MAX_POSTED_MSI_COALESCING_LOOP - 1 loops are executed here.
*/
while (++i < MAX_POSTED_MSI_COALESCING_LOOP) {
- if (!handle_pending_pir(pid->pir64, regs))
+ if (!handle_pending_pir(pid->pir, regs))
break;
}
=20
@@ -475,7 +475,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi_notification)
* process PIR bits one last time such that handling the new interrupts
* are not delayed until the next IRQ.
*/
- handle_pending_pir(pid->pir64, regs);
+ handle_pending_pir(pid->pir, regs);
=20
apic_eoi();
irq_exit();
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index cb4aeab914eb..893e7d06e0e6 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -655,8 +655,9 @@ static u8 count_vectors(void *bitmap)
return count;
}
=20
-bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
+bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr)
{
+ u32 *__pir =3D (void *)pir;
u32 i, vec;
u32 pir_val, irr_val, prev_irr_val;
int max_updated_irr;
@@ -668,10 +669,10 @@ bool __kvm_apic_update_irr(u32 *pir, void *regs, int =
*max_irr)
u32 *p_irr =3D (u32 *)(regs + APIC_IRR + i * 0x10);
=20
irr_val =3D READ_ONCE(*p_irr);
- pir_val =3D READ_ONCE(pir[i]);
+ pir_val =3D READ_ONCE(__pir[i]);
=20
if (pir_val) {
- pir_val =3D xchg(&pir[i], 0);
+ pir_val =3D xchg(&__pir[i], 0);
=20
prev_irr_val =3D irr_val;
do {
@@ -691,7 +692,7 @@ bool __kvm_apic_update_irr(u32 *pir, void *regs, int *m=
ax_irr)
}
EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
=20
-bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
+bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *m=
ax_irr)
{
struct kvm_lapic *apic =3D vcpu->arch.apic;
bool irr_updated =3D __kvm_apic_update_irr(pir, apic->regs, max_irr);
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 1a8553ebdb42..0d41780852e4 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -101,8 +101,8 @@ bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct =
kvm_lapic *source,
int shorthand, unsigned int dest, int dest_mode);
int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
-bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
-bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
+bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr);
+bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *m=
ax_irr);
void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
struct dest_map *dest_map);
diff --git a/arch/x86/kvm/vmx/posted_intr.h b/arch/x86/kvm/vmx/posted_intr.h
index ad9116a99bcc..4ff9d720dec0 100644
--- a/arch/x86/kvm/vmx/posted_intr.h
+++ b/arch/x86/kvm/vmx/posted_intr.h
@@ -18,7 +18,7 @@ static inline int pi_find_highest_vector(struct pi_desc *=
pi_desc)
{
int vec;
=20
- vec =3D find_last_bit((unsigned long *)pi_desc->pir, 256);
+ vec =3D find_last_bit(pi_desc->pir, 256);
return vec < 256 ? vec : -1;
}
=20
--=20
2.49.0.472.ge94155a9ec-goog
From nobody Fri May 9 12:43:02 2025
Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com
[209.85.214.201])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 994B9213230
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:22 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.214.201
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525807; cv=none;
b=P30ZQ37J2unvT4dRPJiSxzEWQmJJ4jhHD73XayBi9nz2OFyCbmTp1+PraDHgO8v6a4Z8nBe+2SVw/ZVW25Ts/aXjQfjyo66d9FalveA1QCAR2+1UjYmpyMLUQ93qfomXZAfH3uvrBCWpBP1Pt+ovt+qUJ6Eq9e6IfgcBIkHzmrQ=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525807; c=relaxed/simple;
bh=5iq6Ej0JukMZOt4v5A++8d64xSPyqQ5v5er7/1iuZW4=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=Wa3Jo+vUt0GU1ipq2PO9quXzc1i/qTqMHRZbrdMMQZHU6R/xHvavAmLqtCaCQp2HwGNH9n74F9fYVYmL/cOgkJCADK5KhiCR5Vvq7cjXw9OQ2mlpYUnDgczZ0Y3EyPJZjBalZHlySbili5tO5V8r6lmaeyswL+KLbEg9ZJkjjWo=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=IB82jXoQ; arc=none smtp.client-ip=209.85.214.201
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="IB82jXoQ"
Received: by mail-pl1-f201.google.com with SMTP id
d9443c01a7336-2255ae39f8fso276975ad.0
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:22 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525802; x=1744130602;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=/XYYrhooXHNQcqBoobC7D5bK0XS2jFQGb7UC9bcI9h8=;
b=IB82jXoQ/BkQnpCN7Rnwso7yq0sh9Olsv/ISZOjrxCNXY38HN21itGuR8GTyHGf5QT
elKTjYZKc0bXe7hovNqFTEKchRz5UlBPzDilS+eSSz4Ek6pGZ+j8pDbPHD7rU/xm2IOp
FfFptLjn4aizDgbDhMESnlL8jF+KDt0ecpZnxYvi9AzUzt1XMMX/5oSc/UHa2owTPg/g
9jVjaJFdqd1DB7wZJHIg3/bY5u1INOUwXBLOlX+j7yuXxFNWOfK8uj53110xYeHxDJ+w
iyv0WPoY+M0BnIZRVGN1LSrtD9FctfBHdKZXyOhcomhuWmiWK6wC7DhjuD5O94ELMmIY
qjyA==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525802; x=1744130602;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=/XYYrhooXHNQcqBoobC7D5bK0XS2jFQGb7UC9bcI9h8=;
b=D2ji8HemsJ/+jv/jsK4wmYIg9IvMfs4vCfZY+fYHIEYrAndeLIMROPd5h5H7/zgBGi
RRPq/+KaJmhORj0mznWSP+YI74/q6jeMUSSrF28Ky9nMWETUKckkUhUtmFxYwfAQGXZo
p9Jmiw3Cw5IzjsDyP8kk94JAW7h2r3CxTYSAD+hcyzKf46ezSQQdODSlqKnBpYRkcmdH
FmqoEi87Z4EEqGpMFtYXzFzCsCSRVqjyMKK131vHcxj8sR67pyE4nuGJ33WiCnjv2LXw
Ml5wz2vq5P7j4WddqHFJ+eSaXym1H4t1/At6HzjxiVcbk+CcIRVpKD120+zfaqzmPhkv
NbBg==
X-Gm-Message-State: AOJu0YyubQf35cp88tW9YP2mJAcoeAnNdYeTNOidRaa13TdGxkw961Zo
lGzTvsgNfBypcqYcJrtZ4yG7uQZkvrXzF4SrcdmKk3NOfMHaU87f+wxIWDYqKiNmWUAKnrr0/31
RKw==
X-Google-Smtp-Source:
AGHT+IFy0IhgEaHcg00977nQlGMuEOMnb3oYwKlOFTc/u3M4G7iMNsSXATt5UTOpWjp44DoW3ZbtcVNrt4s=
X-Received: from pfbfo6.prod.google.com
([2002:a05:6a00:6006:b0:736:3cd5:ba36])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a05:6a00:8186:b0:736:b400:b58f
with SMTP id d2e1a72fcca58-739c3f771bcmr873231b3a.0.1743525801845; Tue, 01
Apr 2025 09:43:21 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:44 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-6-seanjc@google.com>
Subject: [PATCH v2 5/8] KVM: VMX: Process PIR using 64-bit accesses on 64-bit
kernels
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Process the PIR at the natural kernel width, i.e. in 64-bit chunks on
64-bit kernels, so that the worst case of having a posted IRQ in each
chunk of the vIRR only requires 4 loads and xchgs from/to the PIR, not 8.
Deliberately use a "continue" to skip empty entries so that the code is a
carbon copy of handle_pending_pir(), in anticipation of deduplicating KVM
and posted MSI logic.
Suggested-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/lapic.c | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 893e7d06e0e6..e4f182ee9340 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -657,26 +657,32 @@ static u8 count_vectors(void *bitmap)
=20
bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr)
{
- u32 *__pir =3D (void *)pir;
+ unsigned long pir_vals[NR_PIR_WORDS];
+ u32 *__pir =3D (void *)pir_vals;
u32 i, vec;
- u32 pir_val, irr_val, prev_irr_val;
+ u32 irr_val, prev_irr_val;
int max_updated_irr;
=20
max_updated_irr =3D -1;
*max_irr =3D -1;
=20
+ for (i =3D 0; i < NR_PIR_WORDS; i++) {
+ pir_vals[i] =3D READ_ONCE(pir[i]);
+ if (!pir_vals[i])
+ continue;
+
+ pir_vals[i] =3D xchg(&pir[i], 0);
+ }
+
for (i =3D vec =3D 0; i <=3D 7; i++, vec +=3D 32) {
u32 *p_irr =3D (u32 *)(regs + APIC_IRR + i * 0x10);
=20
irr_val =3D READ_ONCE(*p_irr);
- pir_val =3D READ_ONCE(__pir[i]);
-
- if (pir_val) {
- pir_val =3D xchg(&__pir[i], 0);
=20
+ if (__pir[i]) {
prev_irr_val =3D irr_val;
do {
- irr_val =3D prev_irr_val | pir_val;
+ irr_val =3D prev_irr_val | __pir[i];
} while (prev_irr_val !=3D irr_val &&
!try_cmpxchg(p_irr, &prev_irr_val, irr_val));
=20
--=20
2.49.0.472.ge94155a9ec-goog
From nobody Fri May 9 12:43:02 2025
Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com
[209.85.216.74])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D12C2144CF
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:24 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.216.74
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525805; cv=none;
b=JmbC8WdyT8dUyz4qLJTgAcH/vu1vDY/RAEl9TD3C2WYyx+lJraHdDZI8pHBe1a9I17azpQ+aN1Cv4EICbbYzLh9TVlQ/FHvpfrq/162GMQg4i8hSsNTkR2QVMgBXn2DXV+aaBKBTalFnsDFcf0w9QOhgGIGLhAqZHJvPKdcUEpU=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525805; c=relaxed/simple;
bh=0mb7W2KJR+X1+iO3XRU17z9B6gV64MNgKjj7DrBL3rQ=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=Zq53z4uowIdV/kDf39b86wDUxyMrHNcKXGUuy0LabEKw824G0R5JyZt8kmovbbZVN7KMWccyGahcmuaU1S07sIBVhviznIH2b3FFog4K685yasCv9TW3j5cF18PoowZNS1F0/J/Gk41ywQdhbb7a/aB2ebFAJcz0MdFXzJFaNSQ=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=yKTYDGFw; arc=none smtp.client-ip=209.85.216.74
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="yKTYDGFw"
Received: by mail-pj1-f74.google.com with SMTP id
98e67ed59e1d1-2ff6af1e264so735736a91.3
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:24 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525803; x=1744130603;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=JvMZfz//CfX9sBYOfMJB+q+wsvNCB9UZGeb1vhxbwqc=;
b=yKTYDGFw7VHBl+U+Jw+Xp1PqBR+1bhJZkrct3n/fRHAeZAqn8xA30ig0dm58liStjJ
0HI0d0hdELhixyO8n+di9f2jPcc8HHu/PCNKJ3k+aZFWZDapAnmOhEiOb1nj/YAgTdEs
KLBbjsgK0HauVh0/vERpOcvBgPeNChm7TPvHrrjPAdJKtpZgGFiD+KvP4QJhKsMkzGLZ
N6qRoNYFjVc36dLSirXnEVPYfV8m8lW48gFarwsJB1BLqzFS8NwEke1vK2whTWooWi7J
TKKDOH1clXCd/1FTmkQWNvRoCykjVeYGBr+9gV1eH5B8zcWwhSKWkSgGkexkgrkdxKU0
rmGQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525803; x=1744130603;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=JvMZfz//CfX9sBYOfMJB+q+wsvNCB9UZGeb1vhxbwqc=;
b=GYLQtxMXfe5pTw4EDdtv5BHKgNBigxjp8Gxzppe/uVnwL9W9iaBwKtm6ZMKRoOhFRN
LSeJuu9uRIva0x4mFUoXDfNm5EMUlk0Ub/utBkGyK8jddrH562oRQyA589I7Mdf+iWIG
JAa1suhaefjLNbv0jrhdQ2KPbLCO7XHShz2+v01zyUAnFA0WHMmz2POswSr0NJC92/RE
t/duTGHK3UJ9Dcz3NcDQGAgVaD09QNSs2QXXLgNtAOXb+LVcgDm1mcSuLmnV2fBksG+L
SN+vfoGvJelgmI2Rpd0qArSTHNoGiz6TXJEtg/I/lvguXfKmRmoezSJ1T6ukgZi6H3su
GcpQ==
X-Gm-Message-State: AOJu0YyrrROLwcoBdCKgca6BBF46TP6MPNeSwlO/R/BFEQ0myaZU0h51
UEueeegI2TQ9CJleALgTBiMMZ/fbOZmIGFiTc+G2SPkEx0hd7NN4RDmY3PzuhvD3c2AB6PfRt3o
ARA==
X-Google-Smtp-Source:
AGHT+IFappA+693mpg8zPDSbFvdj433IwkFt3wteT5TPuG94UFq5oeeszFM3n1+NCGeGHcm5eLfjft4ZDV0=
X-Received: from pfbhh11.prod.google.com
([2002:a05:6a00:868b:b0:739:485f:c33e])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a05:6a20:9f47:b0:1f5:67e2:7790
with SMTP id adf61e73a8af0-2009f606767mr20650362637.17.1743525803622; Tue, 01
Apr 2025 09:43:23 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:45 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-7-seanjc@google.com>
Subject: [PATCH v2 6/8] KVM: VMX: Isolate pure loads from atomic XCHG when
processing PIR
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Rework KVM's processing of the PIR to use the same algorithm as posted
MSIs, i.e. to do READ(x4) =3D> XCHG(x4) instead of (READ+XCHG)(x4). Given
KVM's long-standing, sub-optimal use of 32-bit accesses to the PIR, it's
safe to say far more thought and investigation was put into handling the
PIR for posted MSIs, i.e. there's no reason to assume KVM's existing
logic is meaningful, let alone superior.
Matching the processing done by posted MSIs will also allow deduplicating
the code between KVM and posted MSIs.
See the comment for handle_pending_pir() added by commit 1b03d82ba15e
("x86/irq: Install posted MSI notification handler") for details on
why isolating loads from XCHG is desirable.
Suggested-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/lapic.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index e4f182ee9340..0463e89376fb 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -657,7 +657,7 @@ static u8 count_vectors(void *bitmap)
=20
bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr)
{
- unsigned long pir_vals[NR_PIR_WORDS];
+ unsigned long pir_vals[NR_PIR_WORDS], pending =3D 0;
u32 *__pir =3D (void *)pir_vals;
u32 i, vec;
u32 irr_val, prev_irr_val;
@@ -668,6 +668,13 @@ bool __kvm_apic_update_irr(unsigned long *pir, void *r=
egs, int *max_irr)
=20
for (i =3D 0; i < NR_PIR_WORDS; i++) {
pir_vals[i] =3D READ_ONCE(pir[i]);
+ pending |=3D pir_vals[i];
+ }
+
+ if (!pending)
+ return false;
+
+ for (i =3D 0; i < NR_PIR_WORDS; i++) {
if (!pir_vals[i])
continue;
=20
--=20
2.49.0.472.ge94155a9ec-goog
From nobody Fri May 9 12:43:02 2025
Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com
[209.85.216.74])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82EE9215F56
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:27 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.216.74
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525808; cv=none;
b=exkU7oQwmM0486+3BxuI5YpV68w/fd9p4QZablGxUmArh/bGIlJevVchqo7Nv2rlqQbEL9MrzM5XRe0OQVDR5+DR4QsYX1R9YRNJeyAsbHtKvtQN6ZFvyEJfBhnnQnqV79XoiSkf/yw7+GQ2JEt4BR3N80fk1f4UNaK1k0OJsAQ=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525808; c=relaxed/simple;
bh=+39fVy6ji7kbX1Wk79JiqH4KHEpEfCwzFOyM5dkWHVQ=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=g46m/4mgtghqxWsUHSSXF5comIuy12Q9Gj9fwAyT1DwhJZG0iAPRm2lSKeDmvIvFsmjJAuTEQIfghEAc9krU6s4IFG+CJtJ/KONkKG/FcT+tn9gy7EY++Z1ZQjtcrjRJAZFaxHmQPmCaD7AMnlXotP9hqq8+ZeT3peU4i9Ho8k4=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=M/3oiPhQ; arc=none smtp.client-ip=209.85.216.74
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="M/3oiPhQ"
Received: by mail-pj1-f74.google.com with SMTP id
98e67ed59e1d1-2ff7f9a0b9bso9141048a91.0
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:27 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525807; x=1744130607;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=7VeOo+YDl1ZaLAjoRUcMX3QDQbr2P1YpT08wmcSjNJ0=;
b=M/3oiPhQKMvRclF7Tg7m0qq5LBKoMhM5lQXQYVVYetodLxjm7HFHekmU6KfYUOM36f
6QA++ysoaTl/vfPcusN4EB1P8auXIoelQoGQl6r8C7fIpw3tgsLHLp9JrcmyocaIjdVo
r355KQ3l7fzZQXZuMSS3o3WP+VDZfvblbqyAypDSnWnhqnwM3bk5upeTqKy+eiU/ODa3
hinQXevTgYEO+nwmGwM4pX49ZVeKfz7ZLutwdQIUf0XP/3i3MXatUXCTbYCWcyp3A8QO
QHyKWvC9NIMg80R0yWffLxwzO1ujR3JOus2PHw09k+tZACEh2T52rMkVdpZppejy0yqO
ZRvQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525807; x=1744130607;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=7VeOo+YDl1ZaLAjoRUcMX3QDQbr2P1YpT08wmcSjNJ0=;
b=nW1YhuD+PL8z24fZpcahoF4rxh4WsiBI5mA5foFju8Nwx8Upnrrv7SFaZLAbeuHT1P
GyI3yRhD+yxGWWAaBWPREnODpSSqw1geyTj14Xr9pJHN+9cgu3PJTISR1Zwchd7FPArZ
Z+xzcBm744rSVRahgDzRCp5eO1MTpKyFuFonl8ghv4f0GDGFfRr/KfB1DFF1igyf3pZK
XFptuc15zoxpSm2ZfEZ/pGUda99N5vZB0956TzKS1RZhYbYKCmpMkz0ZqyHJnK5r+TlR
PyOIxHQQQQ8oTEHPecro4eI581dXDHCUxDPzjuAV1pFUIJKliX/dgNPn2oxWnsDyqh6J
yrwg==
X-Gm-Message-State: AOJu0YzrH5XVvQE5RPBjS9cZUY//1uZzTPurbW4zoYam980Xjp1T7cuZ
bvbglxRkG2JE3LGuWHFHuUD9uF43mfsv6DGS0XgH6RIq98HS5I64SRyMYrf1z+tY+cFVe8l9rfL
MDQ==
X-Google-Smtp-Source:
AGHT+IEFM34tlug3Ergg9oOZ5ia6DKaSJuVy+JKjeggDch7iurgtwMeC43/CRt3s5ueDrR+9rtMhvbS0aMM=
X-Received: from pjvf6.prod.google.com ([2002:a17:90a:da86:b0:2fc:2ee0:d38a])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a17:90b:3d45:b0:2fe:e9c6:689e
with SMTP id 98e67ed59e1d1-305608771admr5940492a91.8.1743525806882; Tue, 01
Apr 2025 09:43:26 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:46 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-8-seanjc@google.com>
Subject: [PATCH v2 7/8] KVM: VMX: Use arch_xchg() when processing PIR to avoid
instrumentation
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Use arch_xchg() when moving IRQs from the PIR to the vIRR, purely to avoid
instrumentation so that KVM is compatible with the needs of posted MSI.
This will allow extracting the core PIR logic to common code and sharing
it between KVM and posted MSI handling.
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/kvm/lapic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 0463e89376fb..13363327ad87 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -678,7 +678,7 @@ bool __kvm_apic_update_irr(unsigned long *pir, void *re=
gs, int *max_irr)
if (!pir_vals[i])
continue;
=20
- pir_vals[i] =3D xchg(&pir[i], 0);
+ pir_vals[i] =3D arch_xchg(&pir[i], 0);
}
=20
for (i =3D vec =3D 0; i <=3D 7; i++, vec +=3D 32) {
--=20
2.49.0.472.ge94155a9ec-goog
From nobody Fri May 9 12:43:02 2025
Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com
[209.85.214.202])
(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4962221931C
for <linux-kernel@vger.kernel.org>; Tue, 1 Apr 2025 16:43:29 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=209.85.214.202
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1743525810; cv=none;
b=K40bCqfo8VJsV+W5C6fgwAGzwYNI8AqmQ9HpK0PfUIqxG19EWQ+SyYDEWRd3YTDSD6H3yBpRoOPFH5FTS6QaiXl7gWWjiVMHlEMgrY361WMn+VHvJ0y+7eusSOfCO3aMHbpLEmOSur5sh1ZUkZ9NQtBkKJxEk1xAVe51QN9d0GY=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1743525810; c=relaxed/simple;
bh=OLOwb1ooeYE8kEqHbAiwmAqVs2RQsyUhuURfPkAdAQg=;
h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From:
To:Cc:Content-Type;
b=bV5LYikjTEvdgm3R015gPoEGV2LZexkyhgSxtvAABeqiIr3oXCEwKOCBjqrTxqVP/EWOoCVKRt9dMhzQiNdesUj63ivwi+mXrCPtoEMhd8k/fPEceVpJoVCbk9IaAg/GJ5L/RXwsehewl49yJvJ3f3mx1NLnuY0S7pprVwmIDiw=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b=lnEeISpW; arc=none smtp.client-ip=209.85.214.202
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=reject dis=none) header.from=google.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=google.com header.i=@google.com
header.b="lnEeISpW"
Received: by mail-pl1-f202.google.com with SMTP id
d9443c01a7336-225429696a9so168194765ad.1
for <linux-kernel@vger.kernel.org>;
Tue, 01 Apr 2025 09:43:29 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=google.com; s=20230601; t=1743525808; x=1744130608;
darn=vger.kernel.org;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:from:to:cc:subject:date:message-id:reply-to;
bh=J4EaWThVax9a+rwMhF6yZ1iQunAjXVQBx8Hy6/tixQ4=;
b=lnEeISpW1dK+cEevA+wWDVeAveNKwsnIhg43db/iYyyEQatGqQXlIvSynAg3xPnT7a
1JxZ1GbD79QXmvPJJgfmceLJUhcLCFcsG1jbQmOoo9aIkqMVAEis7LlWwRtizBuduCwm
8mBuxE10G11ZepnKnNf3RcAPqyNOrqXcnA2KaYQFDmT4aQLUjYDlzP13BPuh+xaL6kak
rs+we2AFZdYVwURJJ/HO7oFmL16W3fqTs7KFWeDgw/1/km1X1ddvDWUkaG3qJEreGfct
TEdw+t+PRA3ed3hWqK04MqDQAPeS6bLnr938k7tLw2aU8wuVxm+AO0A2mhT8/LJ9A9dV
91bA==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
d=1e100.net; s=20230601; t=1743525808; x=1744130608;
h=cc:to:from:subject:message-id:references:mime-version:in-reply-to
:date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id
:reply-to;
bh=J4EaWThVax9a+rwMhF6yZ1iQunAjXVQBx8Hy6/tixQ4=;
b=RFAQgWGE2XXVFpMCW1QmI6DS7iI0Sj43hsm2Nf+SByB8eWJj5U38hrCd+UVkg8V3BQ
U7FdLK36iPXVubK5cYMS1XoAFZy13waxM93NrOxJ9kRcNQGAYVwTk9UQ2Ws5gsho4fPG
xo5wg9pGzviRF/5U3UosrMncV2HxS8ei9YyM9ygoLgzw8FPaezTAwNqAQufYp7dBp2+I
ChiCH9GDuKwyYlZzQax/MDDIbU3/g6LJzVgg9YPh8sV2E2ZMkNhOSS/0tE6dYi2BArBw
1OBi+2J5EYbeP8scPEkvsLZg5FqY3D7Sz8a64MyuzjSj1MiO8UgAp5esYy0iJjBOcSYz
fidg==
X-Gm-Message-State: AOJu0Yxt7kMJfqhHzK6tycLS7FLOhH9fPvYSpDIzvsLZlBXXUZ0UTjLT
LaYywyvenWz+AV84XHu0S2r/OP3Vifi6mf9wwBbhLtXBD0KnkIs64WIk7zpqUfZnnA5lMV/GwLN
vgQ==
X-Google-Smtp-Source:
AGHT+IG+549uJ+p5h+jsssZ8JRnj/shC1446VEr9mloO2RqS2MvoVJe5+Bo4jdQs31e7cn/R3826qBseTE8=
X-Received: from pfbde10.prod.google.com
([2002:a05:6a00:468a:b0:730:7b0c:592c])
(user=seanjc job=prod-delivery.src-stubby-dispatcher) by
2002:a05:6a00:2383:b0:736:34a2:8a18
with SMTP id d2e1a72fcca58-7398044db06mr17829997b3a.24.1743525808635; Tue, 01
Apr 2025 09:43:28 -0700 (PDT)
Reply-To: Sean Christopherson <seanjc@google.com>
Date: Tue, 1 Apr 2025 09:34:47 -0700
In-Reply-To: <20250401163447.846608-1-seanjc@google.com>
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
Mime-Version: 1.0
References: <20250401163447.846608-1-seanjc@google.com>
X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog
Message-ID: <20250401163447.846608-9-seanjc@google.com>
Subject: [PATCH v2 8/8] x86/irq: KVM: Add helper for harvesting PIR to
deduplicate KVM and posted MSIs
From: Sean Christopherson <seanjc@google.com>
To: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
Sean Christopherson <seanjc@google.com>, Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Jim Mattson <jmattson@google.com>
Content-Transfer-Encoding: quoted-printable
Content-Type: text/plain; charset="utf-8"
Now that posted MSI and KVM harvesting of PIR is identical, extract the
code (and posted MSI's wonderful comment) to a common helper.
No functional change intended.
Signed-off-by: Sean Christopherson <seanjc@google.com>
---
arch/x86/include/asm/posted_intr.h | 64 ++++++++++++++++++++++++++++++
arch/x86/kernel/irq.c | 50 ++---------------------
arch/x86/kvm/lapic.c | 16 +-------
3 files changed, 69 insertions(+), 61 deletions(-)
diff --git a/arch/x86/include/asm/posted_intr.h b/arch/x86/include/asm/post=
ed_intr.h
index c3e6e4221a5b..3198e4f217dc 100644
--- a/arch/x86/include/asm/posted_intr.h
+++ b/arch/x86/include/asm/posted_intr.h
@@ -1,8 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _X86_POSTED_INTR_H
#define _X86_POSTED_INTR_H
+
+#include <asm/cmpxchg.h>
+#include <asm/rwonce.h>
#include <asm/irq_vectors.h>
=20
+#include <linux/bitmap.h>
+
#define POSTED_INTR_ON 0
#define POSTED_INTR_SN 1
=20
@@ -26,6 +31,65 @@ struct pi_desc {
u32 rsvd[6];
} __aligned(64);
=20
+/*
+ * De-multiplexing posted interrupts is on the performance path, the code
+ * below is written to optimize the cache performance based on the followi=
ng
+ * considerations:
+ * 1.Posted interrupt descriptor (PID) fits in a cache line that is freque=
ntly
+ * accessed by both CPU and IOMMU.
+ * 2.During software processing of posted interrupts, the CPU needs to do
+ * natural width read and xchg for checking and clearing posted interrupt
+ * request (PIR), a 256 bit field within the PID.
+ * 3.On the other side, the IOMMU does atomic swaps of the entire PID cache
+ * line when posting interrupts and setting control bits.
+ * 4.The CPU can access the cache line a magnitude faster than the IOMMU.
+ * 5.Each time the IOMMU does interrupt posting to the PIR will evict the =
PID
+ * cache line. The cache line states after each operation are as follows,
+ * assuming a 64-bit kernel:
+ * CPU IOMMU PID Cache line state
+ * ---------------------------------------------------------------
+ *...read64 exclusive
+ *...lock xchg64 modified
+ *... post/atomic swap invalid
+ *...-------------------------------------------------------------
+ *
+ * To reduce L1 data cache miss, it is important to avoid contention with
+ * IOMMU's interrupt posting/atomic swap. Therefore, a copy of PIR is used
+ * when processing posted interrupts in software, e.g. to dispatch interru=
pt
+ * handlers for posted MSIs, or to move interrupts from the PIR to the vIRR
+ * in KVM.
+ *
+ * In addition, the code is trying to keep the cache line state consistent
+ * as much as possible. e.g. when making a copy and clearing the PIR
+ * (assuming non-zero PIR bits are present in the entire PIR), it does:
+ * read, read, read, read, xchg, xchg, xchg, xchg
+ * instead of:
+ * read, xchg, read, xchg, read, xchg, read, xchg
+ */
+static __always_inline bool pi_harvest_pir(unsigned long *pir,
+ unsigned long *pir_vals)
+{
+ unsigned long pending =3D 0;
+ int i;
+
+ for (i =3D 0; i < NR_PIR_WORDS; i++) {
+ pir_vals[i] =3D READ_ONCE(pir[i]);
+ pending |=3D pir_vals[i];
+ }
+
+ if (!pending)
+ return false;
+
+ for (i =3D 0; i < NR_PIR_WORDS; i++) {
+ if (!pir_vals[i])
+ continue;
+
+ pir_vals[i] =3D arch_xchg(&pir[i], 0);
+ }
+
+ return true;
+}
+
static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
{
return test_and_set_bit(POSTED_INTR_ON, (unsigned long *)&pi_desc->contro=
l);
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 3753a8acd009..f7c6d94cf070 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -375,58 +375,14 @@ void intel_posted_msi_init(void)
this_cpu_write(posted_msi_pi_desc.ndst, destination);
}
=20
-/*
- * De-multiplexing posted interrupts is on the performance path, the code
- * below is written to optimize the cache performance based on the followi=
ng
- * considerations:
- * 1.Posted interrupt descriptor (PID) fits in a cache line that is freque=
ntly
- * accessed by both CPU and IOMMU.
- * 2.During posted MSI processing, the CPU needs to do 64-bit read and xchg
- * for checking and clearing posted interrupt request (PIR), a 256 bit f=
ield
- * within the PID.
- * 3.On the other side, the IOMMU does atomic swaps of the entire PID cache
- * line when posting interrupts and setting control bits.
- * 4.The CPU can access the cache line a magnitude faster than the IOMMU.
- * 5.Each time the IOMMU does interrupt posting to the PIR will evict the =
PID
- * cache line. The cache line states after each operation are as follows:
- * CPU IOMMU PID Cache line state
- * ---------------------------------------------------------------
- *...read64 exclusive
- *...lock xchg64 modified
- *... post/atomic swap invalid
- *...-------------------------------------------------------------
- *
- * To reduce L1 data cache miss, it is important to avoid contention with
- * IOMMU's interrupt posting/atomic swap. Therefore, a copy of PIR is used
- * to dispatch interrupt handlers.
- *
- * In addition, the code is trying to keep the cache line state consistent
- * as much as possible. e.g. when making a copy and clearing the PIR
- * (assuming non-zero PIR bits are present in the entire PIR), it does:
- * read, read, read, read, xchg, xchg, xchg, xchg
- * instead of:
- * read, xchg, read, xchg, read, xchg, read, xchg
- */
static __always_inline bool handle_pending_pir(unsigned long *pir, struct =
pt_regs *regs)
{
- unsigned long pir_copy[NR_PIR_WORDS], pending =3D 0;
- int i, vec =3D FIRST_EXTERNAL_VECTOR;
+ unsigned long pir_copy[NR_PIR_WORDS];
+ int vec =3D FIRST_EXTERNAL_VECTOR;
=20
- for (i =3D 0; i < NR_PIR_WORDS; i++) {
- pir_copy[i] =3D READ_ONCE(pir[i]);
- pending |=3D pir_copy[i];
- }
-
- if (!pending)
+ if (!pi_harvest_pir(pir, pir_copy))
return false;
=20
- for (i =3D 0; i < NR_PIR_WORDS; i++) {
- if (!pir_copy[i])
- continue;
-
- pir_copy[i] =3D arch_xchg(&pir[i], 0);
- }
-
for_each_set_bit_from(vec, pir_copy, FIRST_SYSTEM_VECTOR)
call_irq_handler(vec, regs);
=20
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 13363327ad87..1c611b84b8ab 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -657,7 +657,7 @@ static u8 count_vectors(void *bitmap)
=20
bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr)
{
- unsigned long pir_vals[NR_PIR_WORDS], pending =3D 0;
+ unsigned long pir_vals[NR_PIR_WORDS];
u32 *__pir =3D (void *)pir_vals;
u32 i, vec;
u32 irr_val, prev_irr_val;
@@ -666,21 +666,9 @@ bool __kvm_apic_update_irr(unsigned long *pir, void *r=
egs, int *max_irr)
max_updated_irr =3D -1;
*max_irr =3D -1;
=20
- for (i =3D 0; i < NR_PIR_WORDS; i++) {
- pir_vals[i] =3D READ_ONCE(pir[i]);
- pending |=3D pir_vals[i];
- }
-
- if (!pending)
+ if (!pi_harvest_pir(pir, pir_vals))
return false;
=20
- for (i =3D 0; i < NR_PIR_WORDS; i++) {
- if (!pir_vals[i])
- continue;
-
- pir_vals[i] =3D arch_xchg(&pir[i], 0);
- }
-
for (i =3D vec =3D 0; i <=3D 7; i++, vec +=3D 32) {
u32 *p_irr =3D (u32 *)(regs + APIC_IRR + i * 0x10);
=20
--=20
2.49.0.472.ge94155a9ec-goog