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Tue, 01 Apr 2025 08:45:48 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang , Frank Li , Marco Felsch , Marc Kleine-Budde Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/6] dt-bindings: bus: add documentation for the IMX AIPSTZ bridge Date: Tue, 1 Apr 2025 11:43:59 -0400 Message-Id: <20250401154404.45932-2-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250401154404.45932-1-laurentiumihalcea111@gmail.com> References: <20250401154404.45932-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea Add documentation for IMX AIPSTZ bridge. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- .../bindings/bus/fsl,imx8mp-aipstz.yaml | 104 ++++++++++++++++++ include/dt-bindings/bus/imx-aipstz.h | 25 +++++ 2 files changed, 129 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz= .yaml create mode 100644 include/dt-bindings/bus/imx-aipstz.h diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml b= /Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml new file mode 100644 index 000000000000..13b7fb39d6ac --- /dev/null +++ b/Documentation/devicetree/bindings/bus/fsl,imx8mp-aipstz.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/fsl,imx8mp-aipstz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Secure AHB to IP Slave bus (AIPSTZ) bridge + +description: + The secure AIPS bridge (AIPSTZ) acts as a bridge for AHB masters issuing + transactions to IP Slave peripherals. Additionally, this module offers a= ccess + control configurations meant to restrict which peripherals a master can + access. + +maintainers: + - Laurentiu Mihalcea + +properties: + compatible: + const: fsl,imx8mp-aipstz + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#access-controller-cells": + const: 3 + description: + The first cell consists of the consumer type (master or peripheral). + The second cell consists of the consumer ID. + The third cell consists of the configuration value. + + ranges: true + +# borrowed from simple-bus.yaml, no additional requirements for children +patternProperties: + "@(0|[1-9a-f][0-9a-f]*)$": + type: object + additionalProperties: true + properties: + reg: + items: + minItems: 2 + maxItems: 4 + minItems: 1 + maxItems: 1024 + ranges: + oneOf: + - items: + minItems: 3 + maxItems: 7 + minItems: 1 + maxItems: 1024 + - $ref: /schemas/types.yaml#/definitions/flag + anyOf: + - required: + - reg + - required: + - ranges + +required: + - compatible + - reg + - power-domains + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + + bus@30df0000 { + compatible =3D "fsl,imx8mp-aipstz"; + reg =3D <0x30df0000 0x10000>; + power-domains =3D <&pgc_audio>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #access-controller-cells =3D <3>; + ranges =3D <0x30c00000 0x30c00000 0x400000>; + + dma-controller@30e00000 { + compatible =3D "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; + reg =3D <0x30e00000 0x10000>; + #dma-cells =3D <3>; + clocks =3D <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, + <&clk IMX8MP_CLK_AUDIO_ROOT>; + clock-names =3D "ipg", "ahb"; + interrupts =3D ; + fsl,sdma-ram-script-name =3D "imx/sdma/sdma-imx7d.bin"; + }; + }; diff --git a/include/dt-bindings/bus/imx-aipstz.h b/include/dt-bindings/bus= /imx-aipstz.h new file mode 100644 index 000000000000..b81b4654e00f --- /dev/null +++ b/include/dt-bindings/bus/imx-aipstz.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2025 NXP + */ + +#ifndef _DT_BINDINGS_BUS_IMX_AIPSTZ_H +#define _DT_BINDINGS_BUS_IMX_AIPSTZ_H + +/* consumer type - master or peripheral */ +#define IMX_AIPSTZ_MASTER 0x0 +#define IMX_AIPSTZ_PERIPH 0x1 + +/* master configuration options */ +#define IMX_AIPSTZ_MPL 0x1 +#define IMX_AIPSTZ_MTW 0x2 +#define IMX_AIPSTZ_MTR 0x4 +#define IMX_AIPSTZ_MBW 0x8 + +/* peripheral configuration options */ +#define IMX_AIPSTZ_TP 0x1 +#define IMX_AIPSTZ_WP 0x2 +#define IMX_AIPSTZ_SP 0x4 +#define IMX_AIPSTZ_BW 0x8 + +#endif /* _DT_BINDINGS_BUS_IMX_AIPSTZ_H */ --=20 2.34.1 From nobody Thu Apr 10 18:06:01 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD39120CCE6; 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charset="utf-8" From: Laurentiu Mihalcea Some DSP instances may have their access to certain peripherals conditioned by a bus access controller such as the one from the AIPSTZ bridge. Add the optional 'access-controllers' property, which may be used in such cases. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/dsp/fsl,dsp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documenta= tion/devicetree/bindings/dsp/fsl,dsp.yaml index b8693e4b4b0d..e610b7636a08 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -91,6 +91,9 @@ properties: - const: runstall - const: softreset =20 + access-controllers: + maxItems: 1 + required: - compatible - reg --=20 2.34.1 From nobody Thu Apr 10 18:06:01 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 672C320D51E; Tue, 1 Apr 2025 15:45:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; 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charset="utf-8" From: Laurentiu Mihalcea The secure AHB to IP Slave (AIPSTZ) bus bridge provides access control configurations meant to restrict access to certain peripherals. Some of the configurations include: 1) Marking masters as trusted for R/W. Based on this (and the configuration of the accessed peripheral), the bridge may choose to abort the R/W transactions issued by certain masters. 2) Allowing/disallowing write accesses to peripherals. Add driver for this IP. Since there's currently no framework for access controllers (and since there's currently no need for having flexibility w.r.t the configurations) all this driver does is it applies a relaxed, "default" configuration, in which all masters are trusted for R/W. Note that some instances of this IP (e.g: AIPSTZ5 on i.MX8MP) may be tied to a power domain and may lose their configuration when the domain is powered off. This is why the configuration has to be restored when the domain is powered on. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea --- drivers/bus/Kconfig | 6 +++ drivers/bus/Makefile | 1 + drivers/bus/imx-aipstz.c | 92 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 99 insertions(+) create mode 100644 drivers/bus/imx-aipstz.c diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index ff669a8ccad9..fe7600283e70 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -87,6 +87,12 @@ config HISILICON_LPC Driver to enable I/O access to devices attached to the Low Pin Count bus on the HiSilicon Hip06/7 SoC. =20 +config IMX_AIPSTZ + tristate "Support for IMX Secure AHB to IP Slave bus (AIPSTZ) bridge" + depends on ARCH_MXC + help + Enable support for IMX AIPSTZ bridge. + config IMX_WEIM bool "Freescale EIM DRIVER" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index cddd4984d6af..8e693fe8a03a 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_FSL_MC_BUS) +=3D fsl-mc/ =20 obj-$(CONFIG_BT1_APB) +=3D bt1-apb.o obj-$(CONFIG_BT1_AXI) +=3D bt1-axi.o +obj-$(CONFIG_IMX_AIPSTZ) +=3D imx-aipstz.o obj-$(CONFIG_IMX_WEIM) +=3D imx-weim.o obj-$(CONFIG_INTEL_IXP4XX_EB) +=3D intel-ixp4xx-eb.o obj-$(CONFIG_MIPS_CDMM) +=3D mips_cdmm.o diff --git a/drivers/bus/imx-aipstz.c b/drivers/bus/imx-aipstz.c new file mode 100644 index 000000000000..44db40dae71b --- /dev/null +++ b/drivers/bus/imx-aipstz.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2025 NXP + */ + +#include +#include +#include +#include +#include +#include + +#define IMX_AIPSTZ_MPR0 0x0 + +struct imx_aipstz_config { + u32 mpr0; +}; + +static void imx_aipstz_apply_default(void __iomem *base, + const struct imx_aipstz_config *default_cfg) +{ + writel(default_cfg->mpr0, base + IMX_AIPSTZ_MPR0); +} + +static int imx_aipstz_probe(struct platform_device *pdev) +{ + const struct imx_aipstz_config *default_cfg; + void __iomem *base; + + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(base)) + return dev_err_probe(&pdev->dev, -ENOMEM, + "failed to get/ioremap AC memory\n"); + + default_cfg =3D of_device_get_match_data(&pdev->dev); + + imx_aipstz_apply_default(base, default_cfg); + + dev_set_drvdata(&pdev->dev, base); + + pm_runtime_set_active(&pdev->dev); + devm_pm_runtime_enable(&pdev->dev); + + return devm_of_platform_populate(&pdev->dev); +} + +static int imx_aipstz_runtime_resume(struct device *dev) +{ + const struct imx_aipstz_config *default_cfg; + void __iomem *base; + + base =3D dev_get_drvdata(dev); + default_cfg =3D of_device_get_match_data(dev); + + /* restore potentially lost configuration during domain power-off */ + imx_aipstz_apply_default(base, default_cfg); + + return 0; +} + +static const struct dev_pm_ops imx_aipstz_pm_ops =3D { + RUNTIME_PM_OPS(NULL, imx_aipstz_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + +/* + * following configuration is equivalent to: + * masters 0-7 =3D> trusted for R/W + use AHB's HPROT[1] to det. privilege + */ +static const struct imx_aipstz_config imx8mp_aipstz_default_cfg =3D { + .mpr0 =3D 0x77777777, +}; + +static const struct of_device_id imx_aipstz_of_ids[] =3D { + { .compatible =3D "fsl,imx8mp-aipstz", .data =3D &imx8mp_aipstz_default_c= fg }, + { } +}; +MODULE_DEVICE_TABLE(of, imx_aipstz_of_ids); + +static struct platform_driver imx_aipstz_of_driver =3D { + .probe =3D imx_aipstz_probe, + .driver =3D { + .name =3D "imx-aipstz", + .of_match_table =3D imx_aipstz_of_ids, + .pm =3D pm_ptr(&imx_aipstz_pm_ops), + }, +}; +module_platform_driver(imx_aipstz_of_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("IMX secure AHB to IP Slave bus (AIPSTZ) bridge driver"= ); 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Tue, 01 Apr 2025 08:45:55 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam , Daniel Baluta , Shengjiu Wang , Frank Li , Marco Felsch , Marc Kleine-Budde Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 4/6] arm64: dts: imx8mp: convert 'aips5' to 'aipstz5' Date: Tue, 1 Apr 2025 11:44:02 -0400 Message-Id: <20250401154404.45932-5-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250401154404.45932-1-laurentiumihalcea111@gmail.com> References: <20250401154404.45932-1-laurentiumihalcea111@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Laurentiu Mihalcea AIPS5 is actually AIPSTZ5 as it offers some security-related configurations. Since these configurations need to be applied before accessing any of the peripherals on the bus, it's better to make AIPSTZ5 be their parent instead of keeping AIPS5 and adding a child node for AIPSTZ5. Also, because of the security configurations, the address space of the bus has to be changed to that of the configuration registers. Finally, since AIPSTZ5 belongs to the AUDIOMIX power domain, add the missing 'power-domains' property. The domain needs to be powered on before attempting to configure the security-related registers. The DT node name is not changed to avoid potential issues with DTs in which this node is referenced. Co-developed-by: Daniel Baluta Signed-off-by: Daniel Baluta Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index ce6793b2d57e..aa7940c65f2d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1399,12 +1399,14 @@ eqos: ethernet@30bf0000 { }; }; =20 - aips5: bus@30c00000 { - compatible =3D "fsl,aips-bus", "simple-bus"; - reg =3D <0x30c00000 0x400000>; + aips5: bus@30df0000 { + compatible =3D "fsl,imx8mp-aipstz"; + reg =3D <0x30df0000 0x10000>; + power-domains =3D <&pgc_audio>; #address-cells =3D <1>; #size-cells =3D <1>; - ranges; + #access-controller-cells =3D <3>; + ranges =3D <0x30c00000 0x30c00000 0x400000>; =20 spba-bus@30c00000 { compatible =3D "fsl,spba-bus", "simple-bus"; --=20 2.34.1 From nobody Thu Apr 10 18:06:01 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6889220E33D; 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charset="utf-8" From: Laurentiu Mihalcea Add header file with master ID definitions for i.MX8MP's AIPSTZ. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-aipstz.h | 25 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 2 files changed, 26 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-aipstz.h diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h b/arch/arm64/boo= t/dts/freescale/imx8mp-aipstz.h new file mode 100644 index 000000000000..23725cdef23b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-aipstz.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX8MP_AIPSTZ_H +#define __IMX8MP_AIPSTZ_H + +#include + +/* master ID definitions */ +#define IMX8MP_AIPSTZ_EDMA 0 /* AUDIOMIX EDMA */ +#define IMX8MP_AIPSTZ_CA53 1 /* Cortex-A53 cluster */ +#define IMX8MP_AIPSTZ_SDMA2 3 /* AUDIOMIX SDMA2 */ +#define IMX8MP_AIPSTZ_SDMA3 3 /* AUDIOMIX SDMA3 */ +#define IMX8MP_AIPSTZ_HIFI4 5 /* HIFI4 DSP */ +#define IMX8MP_AIPSTZ_CM7 6 /* Cortex-M7 */ + +/* helper macros */ +#define IMX8MP_AIPSTZ_HIFI4_T_RW_PL \ + IMX_AIPSTZ_MASTER \ + IMX8MP_AIPSTZ_HIFI4 \ + (IMX_AIPSTZ_MPL | IMX_AIPSTZ_MTW | IMX_AIPSTZ_MTR) + +#endif /* __IMX8MP_AIPSTZ_H */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index aa7940c65f2d..ebbc99f9ceba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -12,6 +12,7 @@ #include #include =20 +#include "imx8mp-aipstz.h" #include "imx8mp-pinfunc.h" =20 / { --=20 2.34.1 From nobody Thu Apr 10 18:06:01 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2838120E717; 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charset="utf-8" From: Laurentiu Mihalcea The DSP needs to access peripherals on AIPSTZ5 (to communicate with the AP using AUDIOMIX MU, for instance). To do so, the security-related registers of the bridge have to be configured before the DSP is started. Enforce a dependency on AIPSTZ5 by adding the 'access-controllers' property to the 'dsp' node. Signed-off-by: Laurentiu Mihalcea Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dt= s/freescale/imx8mp.dtsi index ebbc99f9ceba..f0f0ff5edea6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2425,6 +2425,7 @@ dsp: dsp@3b6e8000 { mboxes =3D <&mu2 2 0>, <&mu2 2 1>, <&mu2 3 0>, <&mu2 3 1>; memory-region =3D <&dsp_reserved>; + access-controllers =3D <&aips5 IMX8MP_AIPSTZ_HIFI4_T_RW_PL>; status =3D "disabled"; }; }; --=20 2.34.1