From nobody Fri Dec 19 14:32:08 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2715020458B for ; Tue, 1 Apr 2025 12:59:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743512361; cv=none; b=DYJdRoEmaE1Pk+g3U9snxEf1kdR1HtnRw7Fm5juMkuzSZrLrvOepuTSFT7L90nhzOV1DslhVt9GRCjz96DrtIywEzOqNy4L9Ggwe4UosKLrwILFvVrA/laXugn/IRXVZPCnZpmo7AJEAS5sgjy6YR0yPXJKq12UMQA7YWAHn0GY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743512361; c=relaxed/simple; bh=vij+eg+HoIyKPFNQ6ksMWa1LqriM7MQpY38tfM+d7Vo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=BYIAthGwyN9ZYH0AWEsMmzBGlPpNSyMsqbnJPr2NF7tja6DXFX9TwSu4zXkBB9XmKOcHlpU6ult+Na55hoq+lV7MBSIE+OCrS/pAb0IqzI6rdAxZqdnjR6F2pJPjESFtXxOEa3CSUKS0xgIjyFxQLJ3UZSYuNynjxpRCw4XnsHM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=HDtCAghC; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="HDtCAghC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1743512359; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4T5YZzFJVFoHxFGDPwj28D6xxyWc9uUCeJgRzddCMdE=; b=HDtCAghC91tQqPWRGzIDfSF7WE/XhIZWDwQUiA96NTUVffx41Qo08ObwhyJ1zMVVUHYPCz ynpv5jwlzH46eFpYamW4gLBWJJ5vC9M3vY82Jnwdch86PTQ+WFfqRMkoUx8C26X/w2zK7x Mg73RwYtZiTyhq5Q0kTdQAy5bFGZXe4= Received: from mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-54-WXLNX-uMPlipBAMXdygAJQ-1; Tue, 01 Apr 2025 08:59:15 -0400 X-MC-Unique: WXLNX-uMPlipBAMXdygAJQ-1 X-Mimecast-MFC-AGG-ID: WXLNX-uMPlipBAMXdygAJQ_1743512354 Received: from mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.15]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 53B481956087; Tue, 1 Apr 2025 12:59:14 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.32.206]) by mx-prod-int-02.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C64871956094; Tue, 1 Apr 2025 12:59:08 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v6 8/8] drm/i915/display: Add drm_panic support for 4-tiling with DPT Date: Tue, 1 Apr 2025 14:51:14 +0200 Message-ID: <20250401125818.333033-9-jfalempe@redhat.com> In-Reply-To: <20250401125818.333033-1-jfalempe@redhat.com> References: <20250401125818.333033-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.15 Content-Type: text/plain; charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements 4-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 76c10555c10e..68deffe3aa9a 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1289,6 +1289,25 @@ static void intel_ytile_set_pixel(struct drm_scanout= _buffer *sb, unsigned int x, iosys_map_wr(&sb->map[0], offset, u32, color); } =20 +static void intel_4tile_set_pixel(struct drm_scanout_buffer *sb, unsigned = int x, unsigned int y, + u32 color) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(sb->width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | = ((x & 0x10) << 3) | ((y & 0x18) << 5); + offset +=3D swizzle * 4; + iosys_map_wr(&sb->map[0], offset, u32, color); +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1323,7 +1342,6 @@ static void (*intel_get_tiling_func(u64 fb_modifier))= (struct drm_scanout_buffer case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: return intel_ytile_set_pixel; - case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_4_TILED: case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: @@ -1333,6 +1351,8 @@ static void (*intel_get_tiling_func(u64 fb_modifier))= (struct drm_scanout_buffer case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return intel_4tile_set_pixel; + case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Yf_TILED: case I915_FORMAT_MOD_Yf_TILED_CCS: default: --=20 2.49.0