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From: Chukun Pan <amadeus@jmu.edu.cn>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Yao Zi <ziyao@disroot.org>,
Rob Herring <robh@kernel.org>,
Chukun Pan <amadeus@jmu.edu.cn>,
Jonas Karlman <jonas@kwiboo.se>,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
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Subject: [PATCH v3 1/2] arm64: dts: rockchip: Add pwm nodes for RK3528
Date: Tue, 1 Apr 2025 20:00:19 +0800
Message-Id: <20250401120020.976343-2-amadeus@jmu.edu.cn>
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Add pwm nodes for RK3528. The PWM core on RK3528 is the same as
RK3328, but the driver does not support interrupts yet.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts=
/rockchip/rk3528.dtsi
index 35704d0be37a..47d4f63f11d3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -465,6 +465,86 @@ uart7: serial@ffa28000 {
status =3D "disabled";
};
=20
+ pwm0: pwm@ffa90000 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa90000 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
+ pwm1: pwm@ffa90010 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa90010 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
+ pwm2: pwm@ffa90020 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa90020 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
+ pwm3: pwm@ffa90030 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa90030 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
+ pwm4: pwm@ffa98000 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa98000 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
+ pwm5: pwm@ffa98010 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa98010 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
+ pwm6: pwm@ffa98020 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa98020 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
+ pwm7: pwm@ffa98030 {
+ compatible =3D "rockchip,rk3528-pwm",
+ "rockchip,rk3328-pwm";
+ reg =3D <0x0 0xffa98030 0x0 0x10>;
+ clocks =3D <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names =3D "pwm", "pclk";
+ #pwm-cells =3D <3>;
+ status =3D "disabled";
+ };
+
saradc: adc@ffae0000 {
compatible =3D "rockchip,rk3528-saradc";
reg =3D <0x0 0xffae0000 0x0 0x10000>;
--=20
2.25.1
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From: Chukun Pan <amadeus@jmu.edu.cn>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Yao Zi <ziyao@disroot.org>,
Rob Herring <robh@kernel.org>,
Chukun Pan <amadeus@jmu.edu.cn>,
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devicetree@vger.kernel.org
Subject: [PATCH v3 2/2] arm64: dts: rockchip: Enable regulators for Radxa E20C
Date: Tue, 1 Apr 2025 20:00:20 +0800
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Enable pwm and fixed regulators for Radxa E20C. The pwm regulator is
used to power the CPU and GPU. Note that the LPDDR4 voltage is 1.1V.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
.../boot/dts/rockchip/rk3528-radxa-e20c.dts | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts b/arch/arm6=
4/boot/dts/rockchip/rk3528-radxa-e20c.dts
index 57a446b5cbd6..14770bd63ae7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
@@ -9,6 +9,7 @@
=20
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
#include "rk3528.dtsi"
=20
/ {
@@ -80,6 +81,26 @@ led-wan {
};
};
=20
+ vdd_0v9: regulator-0v9-vdd {
+ compatible =3D "regulator-fixed";
+ regulator-name =3D "vdd_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt =3D <900000>;
+ regulator-max-microvolt =3D <900000>;
+ vin-supply =3D <&vcc5v0_sys>;
+ };
+
+ vcc_ddr: regulator-1v1-vcc-ddr {
+ compatible =3D "regulator-fixed";
+ regulator-name =3D "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt =3D <1100000>;
+ regulator-max-microvolt =3D <1100000>;
+ vin-supply =3D <&vcc5v0_sys>;
+ };
+
vcc_1v8: regulator-1v8-vcc {
compatible =3D "regulator-fixed";
regulator-name =3D "vcc_1v8";
@@ -108,6 +129,46 @@ vcc5v0_sys: regulator-5v0-vcc-sys {
regulator-min-microvolt =3D <5000000>;
regulator-max-microvolt =3D <5000000>;
};
+
+ vdd_arm: regulator-vdd-arm {
+ compatible =3D "pwm-regulator";
+ pwms =3D <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply =3D <&vcc5v0_sys>;
+ regulator-name =3D "vdd_arm";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt =3D <746000>;
+ regulator-max-microvolt =3D <1201000>;
+ regulator-settling-time-up-us =3D <250>;
+ };
+
+ vdd_logic: regulator-vdd-logic {
+ compatible =3D "pwm-regulator";
+ pwms =3D <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
+ pwm-supply =3D <&vcc5v0_sys>;
+ regulator-name =3D "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt =3D <705000>;
+ regulator-max-microvolt =3D <1006000>;
+ regulator-settling-time-up-us =3D <250>;
+ };
+};
+
+&cpu0 {
+ cpu-supply =3D <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply =3D <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply =3D <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply =3D <&vdd_arm>;
};
=20
&pinctrl {
@@ -132,6 +193,18 @@ wan_led_g: wan-led-g {
};
};
=20
+&pwm1 {
+ pinctrl-names =3D "default";
+ pinctrl-0 =3D <&pwm1m0_pins>;
+ status =3D "okay";
+};
+
+&pwm2 {
+ pinctrl-names =3D "default";
+ pinctrl-0 =3D <&pwm2m0_pins>;
+ status =3D "okay";
+};
+
&saradc {
vref-supply =3D <&vcc_1v8>;
status =3D "okay";
--=20
2.25.1