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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2025 11:40:57.2349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63f9005a-6e92-463c-1166-08dd71121186 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FD.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6299 Content-Type: text/plain; charset="utf-8" Add a apic->teardown() callback to disable Secure AVIC before rebooting into the new kernel. This ensures that the new kernel does not access the old APIC backing page which was allocated by the previous kernel. Such accesses can happen if there are any APIC accesses done during guest boot before Secure AVIC driver probe is done by the new kernel (as Secure AVIC would have remained enabled in the Secure AVIC control msr). Signed-off-by: Neeraj Upadhyay --- Changes since v2: - Change savic_unregister_gpa() interface to allow GPA unregistration only for local CPU. arch/x86/coco/sev/core.c | 25 +++++++++++++++++++++++++ arch/x86/include/asm/apic.h | 1 + arch/x86/include/asm/sev.h | 2 ++ arch/x86/kernel/apic/apic.c | 3 +++ arch/x86/kernel/apic/x2apic_savic.c | 8 ++++++++ 5 files changed, 39 insertions(+) diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index 9ade2b1993ad..2381859491db 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -1588,6 +1588,31 @@ enum es_result savic_register_gpa(u64 gpa) return res; } =20 +enum es_result savic_unregister_gpa(u64 *gpa) +{ + struct ghcb_state state; + struct es_em_ctxt ctxt; + unsigned long flags; + struct ghcb *ghcb; + int ret =3D 0; + + local_irq_save(flags); + + ghcb =3D __sev_get_ghcb(&state); + + vc_ghcb_invalidate(ghcb); + + ghcb_set_rax(ghcb, -1ULL); + ret =3D sev_es_ghcb_hv_call(ghcb, &ctxt, SVM_VMGEXIT_SECURE_AVIC, + SVM_VMGEXIT_SECURE_AVIC_UNREGISTER_GPA, 0); + if (gpa && ret =3D=3D ES_OK) + *gpa =3D ghcb->save.rbx; + __sev_put_ghcb(&state); + + local_irq_restore(flags); + return ret; +} + static void snp_register_per_cpu_ghcb(void) { struct sev_es_runtime_data *data; diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 7616a622248c..0cd9315226d2 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -306,6 +306,7 @@ struct apic { /* Probe, setup and smpboot functions */ int (*probe)(void); void (*setup)(void); + void (*teardown)(void); int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); =20 void (*init_apic_ldr)(void); diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7c942b9c593a..8a08a03183b4 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -484,6 +484,7 @@ int snp_send_guest_request(struct snp_msg_desc *mdesc, = struct snp_guest_req *req void __init snp_secure_tsc_prepare(void); void __init snp_secure_tsc_init(void); enum es_result savic_register_gpa(u64 gpa); +enum es_result savic_unregister_gpa(u64 *gpa); u64 savic_ghcb_msr_read(u32 reg); void savic_ghcb_msr_write(u32 reg, u64 value); =20 @@ -530,6 +531,7 @@ static inline int snp_send_guest_request(struct snp_msg= _desc *mdesc, struct snp_ static inline void __init snp_secure_tsc_prepare(void) { } static inline void __init snp_secure_tsc_init(void) { } static inline enum es_result savic_register_gpa(u64 gpa) { return ES_UNSUP= PORTED; } +static inline enum es_result savic_unregister_gpa(u64 *gpa) { return ES_UN= SUPPORTED; } static inline void savic_ghcb_msr_write(u32 reg, u64 value) { } static inline u64 savic_ghcb_msr_read(u32 reg) { return 0; } =20 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 86f9c3c7df1c..b5236c8c3032 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1169,6 +1169,9 @@ void disable_local_APIC(void) if (!apic_accessible()) return; =20 + if (apic->teardown) + apic->teardown(); + apic_soft_disable(); =20 #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/apic/x2apic_savic.c b/arch/x86/kernel/apic/x2a= pic_savic.c index 9e2a9bdb0762..8cfffdc4cf8b 100644 --- a/arch/x86/kernel/apic/x2apic_savic.c +++ b/arch/x86/kernel/apic/x2apic_savic.c @@ -349,6 +349,13 @@ static void init_apic_page(void) set_reg(APIC_ID, apic_id); } =20 +static void x2apic_savic_teardown(void) +{ + /* Disable Secure AVIC */ + native_wrmsr(MSR_AMD64_SECURE_AVIC_CONTROL, 0, 0); + savic_unregister_gpa(NULL); +} + static void x2apic_savic_setup(void) { void *backing_page; @@ -426,6 +433,7 @@ static struct apic apic_x2apic_savic __ro_after_init = =3D { .probe =3D x2apic_savic_probe, .acpi_madt_oem_check =3D x2apic_savic_acpi_madt_oem_check, .setup =3D x2apic_savic_setup, + .teardown =3D x2apic_savic_teardown, =20 .dest_mode_logical =3D false, =20 --=20 2.34.1