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From: Chukun Pan <amadeus@jmu.edu.cn>
To: Yao Zi <ziyao@disroot.org>
Cc: Rob Herring <robh@kernel.org>,
Chukun Pan <amadeus@jmu.edu.cn>,
Jonas Karlman <jonas@kwiboo.se>,
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Subject: [PATCH v2 1/3] arm64: dts: rockchip: Add missing uart3 interrupt for
RK3528
Date: Tue, 1 Apr 2025 18:00:18 +0800
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The interrupt of uart3 node on rk3528 is missing, fix it.
Fixes: 7983e6c379a9 ("arm64: dts: rockchip: Add base DT for rk3528 SoC")
Reviewed-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts=
/rockchip/rk3528.dtsi
index 26c3559d6a6d..7f1ffd6003f5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -404,9 +404,10 @@ uart2: serial@ffa00000 {
=20
uart3: serial@ffa08000 {
compatible =3D "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg =3D <0x0 0xffa08000 0x0 0x100>;
clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names =3D "baudclk", "apb_pclk";
- reg =3D <0x0 0xffa08000 0x0 0x100>;
+ interrupts =3D <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
--=20
2.25.1
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From: Chukun Pan <amadeus@jmu.edu.cn>
To: Yao Zi <ziyao@disroot.org>
Cc: Rob Herring <robh@kernel.org>,
Chukun Pan <amadeus@jmu.edu.cn>,
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Subject: [PATCH v2 2/3] arm64: dts: rockchip: Add DMA controller for RK3528
Date: Tue, 1 Apr 2025 18:00:19 +0800
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Add DMA controller dt node for RK3528 SoC.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts=
/rockchip/rk3528.dtsi
index 7f1ffd6003f5..c366766ee3f5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -493,6 +493,24 @@ sdhci: mmc@ffbf0000 {
status =3D "disabled";
};
=20
+ dmac: dma-controller@ffd60000 {
+ compatible =3D "arm,pl330", "arm,primecell";
+ reg =3D <0x0 0xffd60000 0x0 0x4000>;
+ clocks =3D <&cru ACLK_DMAC>;
+ clock-names =3D "apb_pclk";
+ interrupts =3D <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ #dma-cells =3D <1>;
+ };
+
pinctrl: pinctrl {
compatible =3D "rockchip,rk3528-pinctrl";
rockchip,grf =3D <&ioc_grf>;
--=20
2.25.1
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From: Chukun Pan <amadeus@jmu.edu.cn>
To: Yao Zi <ziyao@disroot.org>
Cc: Rob Herring <robh@kernel.org>,
Chukun Pan <amadeus@jmu.edu.cn>,
Jonas Karlman <jonas@kwiboo.se>,
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Subject: [PATCH v2 3/3] arm64: dts: rockchip: Add UART DMA support for RK3528
Date: Tue, 1 Apr 2025 18:00:20 +0800
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The UART ports on RK3528 have DMA capability, describe it.
Flow control is optional, so dma-names are not added.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts=
/rockchip/rk3528.dtsi
index c366766ee3f5..35704d0be37a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -375,6 +375,7 @@ uart0: serial@ff9f0000 {
clocks =3D <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 8>, <&dmac 9>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
@@ -386,6 +387,7 @@ uart1: serial@ff9f8000 {
clocks =3D <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 10>, <&dmac 11>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
@@ -397,6 +399,7 @@ uart2: serial@ffa00000 {
clocks =3D <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 12>, <&dmac 13>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
@@ -408,6 +411,7 @@ uart3: serial@ffa08000 {
clocks =3D <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 14>, <&dmac 15>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
@@ -419,6 +423,7 @@ uart4: serial@ffa10000 {
clocks =3D <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 16>, <&dmac 17>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
@@ -430,6 +435,7 @@ uart5: serial@ffa18000 {
clocks =3D <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 18>, <&dmac 19>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
@@ -441,6 +447,7 @@ uart6: serial@ffa20000 {
clocks =3D <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 20>, <&dmac 21>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
@@ -452,6 +459,7 @@ uart7: serial@ffa28000 {
clocks =3D <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names =3D "baudclk", "apb_pclk";
interrupts =3D <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&dmac 22>, <&dmac 23>;
reg-io-width =3D <4>;
reg-shift =3D <2>;
status =3D "disabled";
--=20
2.25.1