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From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Tue, 1 Apr 2025 14:21:45 +0200
Subject: [PATCH v7 1/7] MAINTAINERS: add entry for STM32 OCTO MEMORY
MANAGER driver
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Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin
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CC: <christophe.kerello@foss.st.com>, <linux-kernel@vger.kernel.org>,
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Add myself as STM32 OCTO MEMORY MANAGER maintainer.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5b7e1f9c30f3e45fb85b0d0f58b56db84d986061..830245c8d583c422e869dfe4b5a=
184faaf52b559 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22766,6 +22766,12 @@ L: linux-i2c@vger.kernel.org
S: Maintained
F: drivers/i2c/busses/i2c-stm32*
=20
+ST STM32 OCTO MEMORY MANAGER
+M: Patrice Chotard <patrice.chotard@foss.st.com>
+S: Maintained
+F: Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.y=
aml
+F: drivers/memory/stm32_omm.c
+
ST STM32 SPI DRIVER
M: Alain Volmat <alain.volmat@foss.st.com>
L: linux-spi@vger.kernel.org
--=20
2.25.1
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From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Tue, 1 Apr 2025 14:21:46 +0200
Subject: [PATCH v7 2/7] dt-bindings: memory-controllers: Add STM32 Octo
Memory Manager controller
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To: Krzysztof Kozlowski <krzk@kernel.org>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin
<mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Krzysztof Kozlowski
<krzk+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon
<will@kernel.org>
CC: <christophe.kerello@foss.st.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
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Add bindings for STM32 Octo Memory Manager (OMM) controller.
OMM manages:
- the muxing between 2 OSPI busses and 2 output ports.
There are 4 possible muxing configurations:
- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
output is on port 2
- OSPI1 and OSPI2 are multiplexed over the same output port 1
- swapped mode (no multiplexing), OSPI1 output is on port 2,
OSPI2 output is on port 1
- OSPI1 and OSPI2 are multiplexed over the same output port 2
- the split of the memory area shared between the 2 OSPI instances.
- chip select selection override.
- the time between 2 transactions in multiplexed mode.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
.../memory-controllers/st,stm32mp25-omm.yaml | 227 +++++++++++++++++=
++++
1 file changed, 227 insertions(+)
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32m=
p25-omm.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm3=
2mp25-omm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..c028bc5341f5072afbed1e435b4=
3245952e50300
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm=
.yaml
@@ -0,0 +1,227 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yam=
l#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Octo Memory Manager (OMM)
+
+maintainers:
+ - Patrice Chotard <patrice.chotard@foss.st.com>
+
+description: |
+ The STM32 Octo Memory Manager is a low-level interface that enables an
+ efficient OCTOSPI pin assignment with a full I/O matrix (before alternate
+ function map) and multiplex of single/dual/quad/octal SPI interfaces over
+ the same bus. It Supports up to:
+ - Two single/dual/quad/octal SPI interfaces
+ - Two ports for pin assignment
+
+properties:
+ compatible:
+ const: st,stm32mp25-omm
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ ranges:
+ description: |
+ Reflects the memory layout per OSPI instance.
+ Format:
+ <chip-select> 0 <registers base address> <size>
+ minItems: 2
+ maxItems: 2
+
+ reg:
+ items:
+ - description: OMM registers
+ - description: OMM memory map area
+
+ reg-names:
+ items:
+ - const: regs
+ - const: memory_map
+
+ memory-region:
+ description:
+ Memory region shared between the 2 OCTOSPI instance.
+ One or two phandle to a node describing a memory mapped region
+ depending of child number.
+ minItems: 1
+ maxItems: 2
+
+ memory-region-names:
+ description:
+ Identify to which OSPI instance the memory region belongs to.
+ items:
+ enum: [ospi1, ospi2]
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: omm
+ - const: ospi1
+ - const: ospi2
+
+ resets:
+ minItems: 3
+ maxItems: 3
+
+ reset-names:
+ items:
+ - const: omm
+ - const: ospi1
+ - const: ospi2
+
+ access-controllers:
+ maxItems: 1
+
+ st,syscfg-amcr:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ The Address Mapping Control Register (AMCR) is used to split the 256=
MB
+ memory map area shared between the 2 OSPI instance. The Octo Memory
+ Manager sets the AMCR depending of the memory-region configuration.
+ The memory split bitmask description is:
+ - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped
+ - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes)
+ - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes)
+ - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes)
+ - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes)
+ items:
+ - description: phandle to syscfg
+ - description: register offset within syscfg
+ - description: register bitmask for memory split
+
+ st,omm-req2ack-ns:
+ description:
+ In multiplexed mode (MUXEN =3D 1), this field defines the time in
+ nanoseconds between two transactions.
+ default: 0
+
+ st,omm-cssel-ovr:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Configure the chip select selector override for the 2 OCTOSPIs.
+ - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to =
NCS1
+ - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to =
NCS1
+ - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to =
NCS2
+ - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to =
NCS2
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ st,omm-mux:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Configure the muxing between the 2 OCTOSPIs busses and the 2 output =
ports.
+ - 0: direct mode
+ - 1: mux OCTOSPI1 and OCTOSPI2 to port 1
+ - 2: swapped mode
+ - 3: mux OCTOSPI1 and OCTOSPI2 to port 2
+ minimum: 0
+ maximum: 3
+ default: 0
+
+ power-domains:
+ maxItems: 1
+
+patternProperties:
+ ^spi@[0-9]:
+ type: object
+ $ref: /schemas/spi/st,stm32mp25-ospi.yaml#
+ description: Required spi child node
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - st,syscfg-amcr
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/st,stm32mp25-rcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/st,stm32mp25-rcc.h>
+ ommanager@40500000 {
+ compatible =3D "st,stm32mp25-omm";
+ reg =3D <0x40500000 0x400>, <0x60000000 0x10000000>;
+ reg-names =3D "regs", "memory_map";
+ ranges =3D <0 0 0x40430000 0x400>,
+ <1 0 0x40440000 0x400>;
+ memory-region =3D <&mm_ospi1>, <&mm_ospi2>;
+ memory-region-names =3D "ospi1", "ospi2";
+ pinctrl-0 =3D <&ospi_port1_clk_pins_a
+ &ospi_port1_io03_pins_a
+ &ospi_port1_cs0_pins_a>;
+ pinctrl-1 =3D <&ospi_port1_clk_sleep_pins_a
+ &ospi_port1_io03_sleep_pins_a
+ &ospi_port1_cs0_sleep_pins_a>;
+ pinctrl-names =3D "default", "sleep";
+ clocks =3D <&rcc CK_BUS_OSPIIOM>,
+ <&scmi_clk CK_SCMI_OSPI1>,
+ <&scmi_clk CK_SCMI_OSPI2>;
+ clock-names =3D "omm", "ospi1", "ospi2";
+ resets =3D <&rcc OSPIIOM_R>,
+ <&scmi_reset RST_SCMI_OSPI1>,
+ <&scmi_reset RST_SCMI_OSPI2>;
+ reset-names =3D "omm", "ospi1", "ospi2";
+ access-controllers =3D <&rifsc 111>;
+ power-domains =3D <&CLUSTER_PD>;
+ #address-cells =3D <2>;
+ #size-cells =3D <1>;
+ st,syscfg-amcr =3D <&syscfg 0x2c00 0x7>;
+ st,omm-req2ack-ns =3D <0>;
+ st,omm-mux =3D <0>;
+ st,omm-cssel-ovr =3D <0>;
+
+ spi@0 {
+ compatible =3D "st,stm32mp25-ospi";
+ reg =3D <0 0 0x400>;
+ memory-region =3D <&mm_ospi1>;
+ interrupts =3D <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&hpdma 2 0x62 0x00003121 0x0>,
+ <&hpdma 2 0x42 0x00003112 0x0>;
+ dma-names =3D "tx", "rx";
+ clocks =3D <&scmi_clk CK_SCMI_OSPI1>;
+ resets =3D <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSP=
I1DLL>;
+ access-controllers =3D <&rifsc 74>;
+ power-domains =3D <&CLUSTER_PD>;
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ st,syscfg-dlyb =3D <&syscfg 0x1000>;
+ };
+
+ spi@1 {
+ compatible =3D "st,stm32mp25-ospi";
+ reg =3D <1 0 0x400>;
+ memory-region =3D <&mm_ospi1>;
+ interrupts =3D <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&hpdma 3 0x62 0x00003121 0x0>,
+ <&hpdma 3 0x42 0x00003112 0x0>;
+ dma-names =3D "tx", "rx";
+ clocks =3D <&scmi_clk CK_KER_OSPI2>;
+ resets =3D <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSP=
I1DLL>;
+ access-controllers =3D <&rifsc 75>;
+ power-domains =3D <&CLUSTER_PD>;
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ st,syscfg-dlyb =3D <&syscfg 0x1000>;
+ };
+ };
--=20
2.25.1
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From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Tue, 1 Apr 2025 14:21:47 +0200
Subject: [PATCH v7 3/7] memory: Add STM32 Octo Memory Manager driver
Precedence: bulk
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To: Krzysztof Kozlowski <krzk@kernel.org>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin
<mcoquelin.stm32@gmail.com>,
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Catalin Marinas <catalin.marinas@arm.com>,
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CC: <christophe.kerello@foss.st.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
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definitions=2025-04-01_05,2025-03-27_02,2024-11-22_01
Octo Memory Manager driver (OMM) manages:
- the muxing between 2 OSPI busses and 2 output ports.
There are 4 possible muxing configurations:
- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
output is on port 2
- OSPI1 and OSPI2 are multiplexed over the same output port 1
- swapped mode (no multiplexing), OSPI1 output is on port 2,
OSPI2 output is on port 1
- OSPI1 and OSPI2 are multiplexed over the same output port 2
- the split of the memory area shared between the 2 OSPI instances.
- chip select selection override.
- the time between 2 transactions in multiplexed mode.
- check firewall access.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
drivers/memory/Kconfig | 17 ++
drivers/memory/Makefile | 1 +
drivers/memory/stm32_omm.c | 474 +++++++++++++++++++++++++++++++++++++++++=
++++
3 files changed, 492 insertions(+)
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index c82d8d8a16eaf154c247c0dbb9aff428b7c81402..3a0703fbfee7d1a9467cc748216=
04d3861fb1de0 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -225,6 +225,23 @@ config STM32_FMC2_EBI
devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
SOCs containing the FMC2 External Bus Interface.
=20
+config STM32_OMM
+ tristate "STM32 Octo Memory Manager"
+ depends on SPI_STM32_OSPI || COMPILE_TEST
+ help
+ This driver manages the muxing between the 2 OSPI busses and
+ the 2 output ports. There are 4 possible muxing configurations:
+ - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
+ output is on port 2
+ - OSPI1 and OSPI2 are multiplexed over the same output port 1
+ - swapped mode (no multiplexing), OSPI1 output is on port 2,
+ OSPI2 output is on port 1
+ - OSPI1 and OSPI2 are multiplexed over the same output port 2
+ It also manages :
+ - the split of the memory area shared between the 2 OSPI instances.
+ - chip select selection override.
+ - the time between 2 transactions in multiplexed mode.
+
source "drivers/memory/samsung/Kconfig"
source "drivers/memory/tegra/Kconfig"
=20
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index d2e6ca9abbe0231c14284e3818ce734c618f83d0..c1959661bf63775bdded6dcbe87=
b732883c26135 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_DA8XX_DDRCTL) +=3D da8xx-ddrctl.o
obj-$(CONFIG_PL353_SMC) +=3D pl353-smc.o
obj-$(CONFIG_RENESAS_RPCIF) +=3D renesas-rpc-if.o
obj-$(CONFIG_STM32_FMC2_EBI) +=3D stm32-fmc2-ebi.o
+obj-$(CONFIG_STM32_OMM) +=3D stm32_omm.o
=20
obj-$(CONFIG_SAMSUNG_MC) +=3D samsung/
obj-$(CONFIG_TEGRA_MC) +=3D tegra/
diff --git a/drivers/memory/stm32_omm.c b/drivers/memory/stm32_omm.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a7029e2cb6d770b25339d79e57=
14f376acefeef
--- /dev/null
+++ b/drivers/memory/stm32_omm.c
@@ -0,0 +1,474 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
+ * Author(s): Patrice Chotard <patrice.chotard@foss.st.com> for STMicroele=
ctronics.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bus/stm32_firewall_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define OMM_CR 0
+#define CR_MUXEN BIT(0)
+#define CR_MUXENMODE_MASK GENMASK(1, 0)
+#define CR_CSSEL_OVR_EN BIT(4)
+#define CR_CSSEL_OVR_MASK GENMASK(6, 5)
+#define CR_REQ2ACK_MASK GENMASK(23, 16)
+
+#define OMM_CHILD_NB 2
+#define OMM_CLK_NB 3
+
+struct stm32_omm {
+ struct resource *mm_res;
+ struct clk_bulk_data clk_bulk[OMM_CLK_NB];
+ void __iomem *io_base;
+ u32 cr;
+ u8 nb_child;
+ bool restore_omm;
+};
+
+static int stm32_omm_set_amcr(struct device *dev, bool set)
+{
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+ resource_size_t mm_ospi2_size =3D 0;
+ static const char * const mm_name[] =3D { "ospi1", "ospi2" };
+ struct regmap *syscfg_regmap;
+ struct device_node *node;
+ struct resource res, res1;
+ u32 amcr_base, amcr_mask;
+ int ret, idx;
+ unsigned int i, amcr, read_amcr;
+
+ for (i =3D 0; i < omm->nb_child; i++) {
+ idx =3D of_property_match_string(dev->of_node,
+ "memory-region-names",
+ mm_name[i]);
+ if (idx < 0)
+ continue;
+
+ /* res1 only used on second loop iteration */
+ res1.start =3D res.start;
+ res1.end =3D res.end;
+
+ node =3D of_parse_phandle(dev->of_node, "memory-region", idx);
+ if (!node)
+ continue;
+
+ ret =3D of_address_to_resource(node, 0, &res);
+ if (ret) {
+ dev_err(dev, "unable to resolve memory region\n");
+ return ret;
+ }
+
+ /* check that memory region fits inside OMM memory map area */
+ if (!resource_contains(omm->mm_res, &res)) {
+ dev_err(dev, "%s doesn't fit inside OMM memory map area\n",
+ mm_name[i]);
+ dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res);
+
+ return -EFAULT;
+ }
+
+ if (i =3D=3D 1) {
+ mm_ospi2_size =3D resource_size(&res);
+
+ /* check that OMM memory region 1 doesn't overlap memory region 2 */
+ if (resource_overlaps(&res, &res1)) {
+ dev_err(dev, "OMM memory-region %s overlaps memory region %s\n",
+ mm_name[0], mm_name[1]);
+ dev_err(dev, "%pR overlaps %pR\n", &res1, &res);
+
+ return -EFAULT;
+ }
+ }
+ }
+
+ syscfg_regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscf=
g-amcr");
+ if (IS_ERR(syscfg_regmap))
+ return dev_err_probe(dev, PTR_ERR(syscfg_regmap),
+ "Failed to get st,syscfg-amcr property\n");
+
+ ret =3D of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1,
+ &amcr_base);
+ if (ret)
+ return ret;
+
+ ret =3D of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2,
+ &amcr_mask);
+ if (ret)
+ return ret;
+
+ amcr =3D mm_ospi2_size / SZ_64M;
+
+ if (set)
+ regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr);
+
+ /* read AMCR and check coherency with memory-map areas defined in DT */
+ regmap_read(syscfg_regmap, amcr_base, &read_amcr);
+ read_amcr =3D read_amcr >> (ffs(amcr_mask) - 1);
+
+ if (amcr !=3D read_amcr) {
+ dev_err(dev, "AMCR value not coherent with DT memory-map areas\n");
+ ret =3D -EINVAL;
+ }
+
+ return ret;
+}
+
+static int stm32_omm_toggle_child_clock(struct device *dev, bool enable)
+{
+ /* As there is only 2 children, remember first child in case of error */
+ struct clk *first_child_clk =3D NULL;
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+ u8 i;
+ int ret;
+
+ for (i =3D 0; i < omm->nb_child; i++) {
+ if (enable) {
+ ret =3D clk_prepare_enable(omm->clk_bulk[i + 1].clk);
+ if (ret) {
+ if (first_child_clk)
+ clk_disable_unprepare(first_child_clk);
+
+ dev_err(dev, "Can not enable clock\n");
+ return ret;
+ }
+ } else {
+ clk_disable_unprepare(omm->clk_bulk[i + 1].clk);
+ }
+
+ first_child_clk =3D omm->clk_bulk[i + 1].clk;
+ }
+
+ return 0;
+}
+
+static int stm32_omm_disable_child(struct device *dev)
+{
+ static const char * const resets_name[] =3D {"ospi1", "ospi2"};
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+ struct reset_control *reset;
+ int ret;
+ u8 i;
+
+ ret =3D stm32_omm_toggle_child_clock(dev, true);
+ if (!ret)
+ return ret;
+
+ for (i =3D 0; i < omm->nb_child; i++) {
+ reset =3D reset_control_get_exclusive(dev, resets_name[i]);
+ if (IS_ERR(reset)) {
+ dev_err(dev, "Can't get %s reset\n", resets_name[i]);
+ return PTR_ERR(reset);
+ };
+
+ /* reset OSPI to ensure CR_EN bit is set to 0 */
+ reset_control_assert(reset);
+ udelay(2);
+ reset_control_deassert(reset);
+
+ reset_control_put(reset);
+ }
+
+ return stm32_omm_toggle_child_clock(dev, false);
+}
+
+static int stm32_omm_configure(struct device *dev)
+{
+ static const char * const clocks_name[] =3D {"omm", "ospi1", "ospi2"};
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+ unsigned long clk_rate_max =3D 0;
+ u32 mux =3D 0;
+ u32 cssel_ovr =3D 0;
+ u32 req2ack =3D 0;
+ struct reset_control *rstc;
+ unsigned long clk_rate;
+ int ret;
+ u8 i;
+
+ for (i =3D 0; i < OMM_CLK_NB; i++)
+ omm->clk_bulk[i].id =3D clocks_name[i];
+
+ /* retrieve OMM, OSPI1 and OSPI2 clocks */
+ ret =3D devm_clk_bulk_get(dev, OMM_CLK_NB, omm->clk_bulk);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to get OMM/OSPI's clocks\n");
+
+ /* Ensure both OSPI instance are disabled before configuring OMM */
+ ret =3D stm32_omm_disable_child(dev);
+ if (ret)
+ return ret;
+
+ ret =3D pm_runtime_resume_and_get(dev);
+ if (ret < 0)
+ return ret;
+
+ /* parse children's clock */
+ for (i =3D 1; i <=3D omm->nb_child; i++) {
+ clk_rate =3D clk_get_rate(omm->clk_bulk[i].clk);
+ if (!clk_rate) {
+ dev_err(dev, "Invalid clock rate\n");
+ goto err_clk_disable;
+ }
+
+ if (clk_rate > clk_rate_max)
+ clk_rate_max =3D clk_rate;
+ }
+
+ rstc =3D devm_reset_control_get_exclusive(dev, "omm");
+ if (IS_ERR(rstc))
+ return dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n");
+
+ reset_control_assert(rstc);
+ udelay(2);
+ reset_control_deassert(rstc);
+
+ omm->cr =3D readl_relaxed(omm->io_base + OMM_CR);
+ /* optional */
+ ret =3D of_property_read_u32(dev->of_node, "st,omm-mux", &mux);
+ if (!ret) {
+ if (mux & CR_MUXEN) {
+ ret =3D of_property_read_u32(dev->of_node, "st,omm-req2ack-ns",
+ &req2ack);
+ if (!ret && !req2ack) {
+ req2ack =3D DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1;
+
+ if (req2ack > 256)
+ req2ack =3D 256;
+ }
+
+ req2ack =3D FIELD_PREP(CR_REQ2ACK_MASK, req2ack);
+
+ omm->cr &=3D ~CR_REQ2ACK_MASK;
+ omm->cr |=3D FIELD_PREP(CR_REQ2ACK_MASK, req2ack);
+
+ /*
+ * If the mux is enabled, the 2 OSPI clocks have to be
+ * always enabled
+ */
+ ret =3D stm32_omm_toggle_child_clock(dev, true);
+ if (ret)
+ goto err_clk_disable;
+ }
+
+ omm->cr &=3D ~CR_MUXENMODE_MASK;
+ omm->cr |=3D FIELD_PREP(CR_MUXENMODE_MASK, mux);
+ }
+
+ /* optional */
+ ret =3D of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr=
);
+ if (!ret) {
+ omm->cr &=3D ~CR_CSSEL_OVR_MASK;
+ omm->cr |=3D FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr);
+ omm->cr |=3D CR_CSSEL_OVR_EN;
+ }
+
+ omm->restore_omm =3D true;
+ writel_relaxed(omm->cr, omm->io_base + OMM_CR);
+
+ ret =3D stm32_omm_set_amcr(dev, true);
+
+err_clk_disable:
+ pm_runtime_put_sync_suspend(dev);
+
+ return ret;
+}
+
+static int stm32_omm_check_access(struct device_node *np)
+{
+ struct stm32_firewall firewall;
+ int ret;
+
+ ret =3D stm32_firewall_get_firewall(np, &firewall, 1);
+ if (ret)
+ return ret;
+
+ return stm32_firewall_grant_access(&firewall);
+}
+
+static int stm32_omm_probe(struct platform_device *pdev)
+{
+ struct device *dev =3D &pdev->dev;
+ u8 child_access_granted =3D 0;
+ struct stm32_omm *omm;
+ int ret;
+
+ omm =3D devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL);
+ if (!omm)
+ return -ENOMEM;
+
+ omm->io_base =3D devm_platform_ioremap_resource_byname(pdev, "regs");
+ if (IS_ERR(omm->io_base))
+ return PTR_ERR(omm->io_base);
+
+ omm->mm_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "memor=
y_map");
+ if (IS_ERR(omm->mm_res))
+ return PTR_ERR(omm->mm_res);
+
+ /* check child's access */
+ for_each_child_of_node_scoped(dev->of_node, child) {
+ if (omm->nb_child >=3D OMM_CHILD_NB) {
+ dev_err(dev, "Bad DT, found too much children\n");
+ return -E2BIG;
+ }
+
+ if (!of_device_is_compatible(child, "st,stm32mp25-omi"))
+ return -EINVAL;
+
+ ret =3D stm32_omm_check_access(child);
+ if (ret < 0 && ret !=3D -EACCES)
+ return ret;
+
+ if (!ret)
+ child_access_granted++;
+
+ omm->nb_child++;
+ }
+
+ if (omm->nb_child !=3D OMM_CHILD_NB)
+ return -EINVAL;
+
+ platform_set_drvdata(pdev, omm);
+
+ pm_runtime_enable(dev);
+
+ /* check if OMM's resource access is granted */
+ ret =3D stm32_omm_check_access(dev->of_node);
+ if (ret < 0 && ret !=3D -EACCES)
+ goto error;
+
+ if (!ret && child_access_granted =3D=3D OMM_CHILD_NB) {
+ ret =3D stm32_omm_configure(dev);
+ if (ret)
+ goto error;
+ } else {
+ dev_dbg(dev, "Octo Memory Manager resource's access not granted\n");
+ /*
+ * AMCR can't be set, so check if current value is coherent
+ * with memory-map areas defined in DT
+ */
+ ret =3D stm32_omm_set_amcr(dev, false);
+ if (ret)
+ goto error;
+ }
+
+ ret =3D of_platform_populate(dev->of_node, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "Failed to create Octo Memory Manager child\n");
+ of_platform_depopulate(dev);
+ ret =3D -EINVAL;
+ goto error;
+ }
+
+ return ret;
+
+error:
+ pm_runtime_disable(dev);
+
+ return ret;
+
+}
+
+static void stm32_omm_remove(struct platform_device *pdev)
+{
+ struct stm32_omm *omm =3D platform_get_drvdata(pdev);
+
+ of_platform_depopulate(&pdev->dev);
+ if (omm->cr & CR_MUXEN)
+ stm32_omm_toggle_child_clock(&pdev->dev, false);
+
+ pm_runtime_disable(&pdev->dev);
+}
+
+static const struct of_device_id stm32_omm_of_match[] =3D {
+ { .compatible =3D "st,stm32mp25-omm", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, stm32_omm_of_match);
+
+static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev)
+{
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+
+ clk_disable_unprepare(omm->clk_bulk[0].clk);
+
+ return 0;
+}
+
+static int __maybe_unused stm32_omm_runtime_resume(struct device *dev)
+{
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+
+ return clk_prepare_enable(omm->clk_bulk[0].clk);
+}
+
+static int __maybe_unused stm32_omm_suspend(struct device *dev)
+{
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+
+ if (omm->restore_omm && omm->cr & CR_MUXEN)
+ stm32_omm_toggle_child_clock(dev, false);
+
+ return pinctrl_pm_select_sleep_state(dev);
+}
+
+static int __maybe_unused stm32_omm_resume(struct device *dev)
+{
+ struct stm32_omm *omm =3D dev_get_drvdata(dev);
+ int ret;
+
+ pinctrl_pm_select_default_state(dev);
+
+ if (!omm->restore_omm)
+ return 0;
+
+ /* Ensure both OSPI instance are disabled before configuring OMM */
+ ret =3D stm32_omm_disable_child(dev);
+ if (ret)
+ return ret;
+
+ ret =3D pm_runtime_resume_and_get(dev);
+ if (ret < 0)
+ return ret;
+
+ writel_relaxed(omm->cr, omm->io_base + OMM_CR);
+ ret =3D stm32_omm_set_amcr(dev, true);
+ pm_runtime_put_sync_suspend(dev);
+ if (ret)
+ return ret;
+
+ if (omm->cr & CR_MUXEN)
+ ret =3D stm32_omm_toggle_child_clock(dev, true);
+
+ return ret;
+}
+
+static const struct dev_pm_ops stm32_omm_pm_ops =3D {
+ SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend,
+ stm32_omm_runtime_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume)
+};
+
+static struct platform_driver stm32_omm_driver =3D {
+ .probe =3D stm32_omm_probe,
+ .remove =3D stm32_omm_remove,
+ .driver =3D {
+ .name =3D "stm32-omm",
+ .of_match_table =3D stm32_omm_of_match,
+ .pm =3D &stm32_omm_pm_ops,
+ },
+};
+module_platform_driver(stm32_omm_driver);
+
+MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver");
+MODULE_LICENSE("GPL");
--=20
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From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Tue, 1 Apr 2025 14:21:48 +0200
Subject: [PATCH v7 4/7] arm64: dts: st: Add OMM node on stm32mp251
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To: Krzysztof Kozlowski <krzk@kernel.org>, Rob Herring <robh@kernel.org>,
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<mcoquelin.stm32@gmail.com>,
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CC: <christophe.kerello@foss.st.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
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Add Octo Memory Manager (OMM) entry on stm32mp251 and its two
OSPI instance.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 54 ++++++++++++++++++++++++++++++=
++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s=
t/stm32mp251.dtsi
index f3c6cdfd7008c5b736ba75f5210d0eddb5b43489..73b573ff7f638f75800bc87a7ee=
d480eda259b15 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -768,6 +768,60 @@ rng: rng@42020000 {
status =3D "disabled";
};
=20
+ ommanager: ommanager@40500000 {
+ compatible =3D "st,stm32mp25-omm";
+ reg =3D <0x40500000 0x400>, <0x60000000 0x10000000>;
+ reg-names =3D "regs", "memory_map";
+ ranges =3D <0 0 0x40430000 0x400>,
+ <1 0 0x40440000 0x400>;
+ clocks =3D <&rcc CK_BUS_OSPIIOM>,
+ <&scmi_clk CK_SCMI_OSPI1>,
+ <&scmi_clk CK_SCMI_OSPI2>;
+ clock-names =3D "omm", "ospi1", "ospi2";
+ resets =3D <&rcc OSPIIOM_R>,
+ <&scmi_reset RST_SCMI_OSPI1>,
+ <&scmi_reset RST_SCMI_OSPI2>;
+ reset-names =3D "omm", "ospi1", "ospi2";
+ access-controllers =3D <&rifsc 111>;
+ power-domains =3D <&CLUSTER_PD>;
+ #address-cells =3D <2>;
+ #size-cells =3D <1>;
+ st,syscfg-amcr =3D <&syscfg 0x2c00 0x7>;
+ status =3D "disabled";
+
+ ospi1: spi@0 {
+ compatible =3D "st,stm32mp25-ospi";
+ reg =3D <0 0 0x400>;
+ interrupts =3D <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&hpdma 2 0x62 0x00003121>,
+ <&hpdma 2 0x42 0x00003112>;
+ dma-names =3D "tx", "rx";
+ clocks =3D <&scmi_clk CK_SCMI_OSPI1>;
+ resets =3D <&scmi_reset RST_SCMI_OSPI1>,
+ <&scmi_reset RST_SCMI_OSPI1DLL>;
+ access-controllers =3D <&rifsc 74>;
+ power-domains =3D <&CLUSTER_PD>;
+ st,syscfg-dlyb =3D <&syscfg 0x1000>;
+ status =3D "disabled";
+ };
+
+ ospi2: spi@1 {
+ compatible =3D "st,stm32mp25-ospi";
+ reg =3D <1 0 0x400>;
+ interrupts =3D <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ dmas =3D <&hpdma 3 0x62 0x00003121>,
+ <&hpdma 3 0x42 0x00003112>;
+ dma-names =3D "tx", "rx";
+ clocks =3D <&scmi_clk CK_SCMI_OSPI2>;
+ resets =3D <&scmi_reset RST_SCMI_OSPI2>,
+ <&scmi_reset RST_SCMI_OSPI2DLL>;
+ access-controllers =3D <&rifsc 75>;
+ power-domains =3D <&CLUSTER_PD>;
+ st,syscfg-dlyb =3D <&syscfg 0x1400>;
+ status =3D "disabled";
+ };
+ };
+
spi8: spi@46020000 {
#address-cells =3D <1>;
#size-cells =3D <0>;
--=20
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From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Tue, 1 Apr 2025 14:21:49 +0200
Subject: [PATCH v7 5/7] arm64: dts: st: Add ospi port1 pinctrl entries in
stm32mp25-pinctrl.dtsi
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To: Krzysztof Kozlowski <krzk@kernel.org>, Rob Herring <robh@kernel.org>,
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definitions=2025-04-01_05,2025-03-27_02,2024-11-22_01
Add pinctrl entry related to OSPI's port1 in stm32mp25-pinctrl.dtsi
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 51 +++++++++++++++++++++++=
++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo=
t/dts/st/stm32mp25-pinctrl.dtsi
index 8fdd5f020425d53eefa724de9c23ec0ca211ab7f..cf5be316de2613e7d7050374c9a=
57fd95020d715 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -101,6 +101,57 @@ pins2 {
};
};
=20
+ ospi_port1_clk_pins_a: ospi-port1-clk-0 {
+ pins {
+ pinmux =3D <STM32_PINMUX('D', 0, AF10)>; /* OSPI1_CLK */
+ bias-disable;
+ drive-push-pull;
+ slew-rate =3D <2>;
+ };
+ };
+
+ ospi_port1_clk_sleep_pins_a: ospi-port1-clk-sleep-0 {
+ pins {
+ pinmux =3D <STM32_PINMUX('D', 0, ANALOG)>; /* OSPI1_CLK */
+ };
+ };
+
+ ospi_port1_cs0_pins_a: ospi-port1-cs0-0 {
+ pins {
+ pinmux =3D <STM32_PINMUX('D', 3, AF10)>; /* OSPI_NCS0 */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate =3D <0>;
+ };
+ };
+
+ ospi_port1_cs0_sleep_pins_a: ospi-port1-cs0-sleep-0 {
+ pins {
+ pinmux =3D <STM32_PINMUX('D', 3, ANALOG)>; /* OSPI_NCS0 */
+ };
+ };
+
+ ospi_port1_io03_pins_a: ospi-port1-io03-0 {
+ pins {
+ pinmux =3D <STM32_PINMUX('D', 4, AF10)>, /* OSPI_IO0 */
+ <STM32_PINMUX('D', 5, AF10)>, /* OSPI_IO1 */
+ <STM32_PINMUX('D', 6, AF10)>, /* OSPI_IO2 */
+ <STM32_PINMUX('D', 7, AF10)>; /* OSPI_IO3 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate =3D <0>;
+ };
+ };
+
+ ospi_port1_io03_sleep_pins_a: ospi-port1-io03-sleep-0 {
+ pins {
+ pinmux =3D <STM32_PINMUX('D', 4, ANALOG)>, /* OSPI_IO0 */
+ <STM32_PINMUX('D', 5, ANALOG)>, /* OSPI_IO1 */
+ <STM32_PINMUX('D', 6, ANALOG)>, /* OSPI_IO2 */
+ <STM32_PINMUX('D', 7, ANALOG)>; /* OSPI_IO3 */
+ };
+ };
+
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
pinmux =3D <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
--=20
2.25.1
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From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Tue, 1 Apr 2025 14:21:50 +0200
Subject: [PATCH v7 6/7] arm64: dts: st: Add SPI NOR flash support on
stm32mp257f-ev1 board
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References: <20250401-upstream_ospi_v6-v7-0-0ef28513ed81@foss.st.com>
In-Reply-To: <20250401-upstream_ospi_v6-v7-0-0ef28513ed81@foss.st.com>
To: Krzysztof Kozlowski <krzk@kernel.org>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin
<mcoquelin.stm32@gmail.com>,
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<krzk+dt@kernel.org>,
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CC: <christophe.kerello@foss.st.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
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definitions=2025-04-01_05,2025-03-27_02,2024-11-22_01
Add SPI NOR flash nor support on stm32mp257f-ev1 board.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 32 ++++++++++++++++++++++++++=
++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d=
ts/st/stm32mp257f-ev1.dts
index 1b88485a62a1f837770654eee6c970208fef6edc..9d1a1155e36ccc283cb73e51b91=
f3200ee54a4aa 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -80,6 +80,11 @@ fw@80000000 {
reg =3D <0x0 0x80000000 0x0 0x4000000>;
no-map;
};
+
+ mm_ospi1: mm-ospi@60000000 {
+ reg =3D <0x0 0x60000000 0x0 0x10000000>;
+ no-map;
+ };
};
};
=20
@@ -190,6 +195,33 @@ &i2c8 {
status =3D "disabled";
};
=20
+&ommanager {
+ memory-region =3D <&mm_ospi1>;
+ pinctrl-0 =3D <&ospi_port1_clk_pins_a
+ &ospi_port1_io03_pins_a
+ &ospi_port1_cs0_pins_a>;
+ pinctrl-1 =3D <&ospi_port1_clk_sleep_pins_a
+ &ospi_port1_io03_sleep_pins_a
+ &ospi_port1_cs0_sleep_pins_a>;
+ pinctrl-names =3D "default", "sleep";
+ status =3D "okay";
+
+ spi@0 {
+ #address-cells =3D <1>;
+ #size-cells =3D <0>;
+ memory-region =3D <&mm_ospi1>;
+ status =3D "okay";
+
+ flash0: flash@0 {
+ compatible =3D "jedec,spi-nor";
+ reg =3D <0>;
+ spi-rx-bus-width =3D <4>;
+ spi-tx-bus-width =3D <4>;
+ spi-max-frequency =3D <50000000>;
+ };
+ };
+};
+
&rtc {
status =3D "okay";
};
--=20
2.25.1
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From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: Tue, 1 Apr 2025 14:21:51 +0200
Subject: [PATCH v7 7/7] arm64: defconfig: Enable STM32 Octo Memory Manager
and OcstoSPI driver
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To: Krzysztof Kozlowski <krzk@kernel.org>, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maxime Coquelin
<mcoquelin.stm32@gmail.com>,
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<will@kernel.org>
CC: <christophe.kerello@foss.st.com>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
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definitions=2025-04-01_05,2025-03-27_02,2024-11-22_01
Enable STM32 OctoSPI driver.
Enable STM32 Octo Memory Manager (OMM) driver which is needed
for OSPI usage on STM32MP257F-EV1 board.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index bde1287ad9a7a1341162b817873eb651bb310d52..3674d9138bae6deba19c0d13586=
aa6e1de6750c5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -580,6 +580,7 @@ CONFIG_SPI_QUP=3Dy
CONFIG_SPI_QCOM_GENI=3Dm
CONFIG_SPI_S3C64XX=3Dy
CONFIG_SPI_SH_MSIOF=3Dm
+CONFIG_SPI_STM32_OSPI=3Dm
CONFIG_SPI_SUN6I=3Dy
CONFIG_SPI_TEGRA210_QUAD=3Dm
CONFIG_SPI_TEGRA114=3Dm
@@ -1518,6 +1519,7 @@ CONFIG_EXTCON_USB_GPIO=3Dy
CONFIG_EXTCON_USBC_CROS_EC=3Dy
CONFIG_FSL_IFC=3Dy
CONFIG_RENESAS_RPCIF=3Dm
+CONFIG_STM32_OMM=3Dm
CONFIG_IIO=3Dy
CONFIG_EXYNOS_ADC=3Dy
CONFIG_IMX8QXP_ADC=3Dm
--=20
2.25.1