From nobody Wed May  7 05:15:22 2025
Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com
 [209.85.218.42])
	(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
	(No client certificate requested)
	by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1A1D1F03E0
	for <linux-kernel@vger.kernel.org>; Tue,  1 Apr 2025 10:11:11 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
 arc=none smtp.client-ip=209.85.218.42
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
	t=1743502273; cv=none;
 b=PB4rQaN9Ddaz564mNyb0aFIcS46Xz3OCilhrxVJWzm9kdTDKhLfFXcoTqEc1RCWQ7Y7MZdEmQbDgcDQYoVjDTJPp1j/PuVHfwAj97TkPod8QEBAdrC4x+oxLRe8bxqOMnZbdbehVzNchWVRvxEPIblFgm+51qNiW/0/sb7lQnaI=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
	s=arc-20240116; t=1743502273; c=relaxed/simple;
	bh=ri0c6XAKIbAL5r1pMx1YsjfpBuk6BBaZV7LqaDJixho=;
	h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:
	 In-Reply-To:To:Cc;
 b=rHPJnUVqA0SVdoy+ncScWzkBB9e6Iz3+1H+TPG5VhwYT8qyQUm7RgiYv5gIaSY6UEYyyM47uqHn68w+IW5MmhgPGqw4UKM1fp23CBCM0EfwrzEGf0XcWWLewp/XCfRF6sYZyLrdCcFDWaL0AgfDQ+2bf2xQi8E/5RWkgDBcxKQU=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
 dmarc=pass (p=none dis=none) header.from=linaro.org;
 spf=pass smtp.mailfrom=linaro.org;
 dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org
 header.b=kAQ9TJw9; arc=none smtp.client-ip=209.85.218.42
Authentication-Results: smtp.subspace.kernel.org;
 dmarc=pass (p=none dis=none) header.from=linaro.org
Authentication-Results: smtp.subspace.kernel.org;
 spf=pass smtp.mailfrom=linaro.org
Authentication-Results: smtp.subspace.kernel.org;
	dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org
 header.b="kAQ9TJw9"
Received: by mail-ej1-f42.google.com with SMTP id
 a640c23a62f3a-aaee2c5ee6eso806267066b.1
        for <linux-kernel@vger.kernel.org>;
 Tue, 01 Apr 2025 03:11:11 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=linaro.org; s=google; t=1743502270; x=1744107070;
 darn=vger.kernel.org;
        h=cc:to:in-reply-to:references:message-id:content-transfer-encoding
         :mime-version:subject:date:from:from:to:cc:subject:date:message-id
         :reply-to;
        bh=f0fLcWG3xRCCoczcLQcRJk5lZ+cdqHvZLEk7m94iuVA=;
        b=kAQ9TJw9GuspSLgSC2f2kFrc8YWz0y5QB39dvHfXL0rItj4MT9bhCXIoc5qUBjzjnY
         z7CWPKC9TX3sRuJZVJ6+cRTsN/rJUW0dJ4zuaOo/odFW9qnhOP40aUG1c4bDc6556KYz
         2tU4m+dENAgd4Bd+bvu09Oqm9nQ2fqa5kgMtwwUmuu9IYCK3TRefc/vy9Ou/KmCaAuvZ
         DhAFSqzE+Il4/WLCvtYT/NV5FFHft5nfbVXfdB7snNgSyObEe30iKWIbWyJI5P7jKAWu
         BjCFirZ59QKtCE3PansEfCPvqxccFTCBt2lG7eYruN4/MHRXWKok+JaZHM818haualK8
         MFhw==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=1e100.net; s=20230601; t=1743502270; x=1744107070;
        h=cc:to:in-reply-to:references:message-id:content-transfer-encoding
         :mime-version:subject:date:from:x-gm-message-state:from:to:cc
         :subject:date:message-id:reply-to;
        bh=f0fLcWG3xRCCoczcLQcRJk5lZ+cdqHvZLEk7m94iuVA=;
        b=X0FCB8pCsYn1zfxsJEUmLAKFcsi4PpN2r0DMfPFwGGgpclrQuORrXG5Ya23uJmMlRK
         E6hYAtLEva5lacV9YTfI+2+fTyWlS+KoPE7UTwLiAnepvxw5698k/zsIwPkazyBQfmmY
         I3Xx+HO0sVKP/LK4LJmKhopRk77cdJJsCdGkxC9tbPuma5+xhMYy5636zYYq4t6DyvJh
         6PBrk/CBZdJU1hs0rm/no7XV9vvyT1vUfpgYgAJfIG/FhE1u+jJ+zldcpNhrk5NER/HZ
         S7y58YXzbNSCCJ5wokY6KEZ6U/xlkX3XUpUdYtNOGfafuaTp/l3jd9KqH8tPumFPC3SA
         /7QQ==
X-Forwarded-Encrypted: i=1;
 AJvYcCW/rqi6KBm7aPybb2s4YT4OKAhyAZKpx2GZmHd2IvKttiJsfjxsgnGwb9ZdJjynA2idjINONJTrVu7PIlw=@vger.kernel.org
X-Gm-Message-State: AOJu0YySVVOYCVUGU6KlwCAki4QuFLYlcwj5YwDzgoDr5zYft+kkUEXo
	Q1BUXkTz57SdQuT59jiMWFsvxj8esu5HgG+l6BA71t7dWzN6p6c92c+niPkfYPQ=
X-Gm-Gg: ASbGnctFWy26ClHS0ZHRwunY3MAdxF1yTRHnT4i8LPiPVbtqWmcDi227E2FikK3McCU
	wIEeaxsNSsemVQFJDwU2Wt0Zh4avEL1VF/YpLUExUVtO/T6MgGhmttFtVWzCdwOS7Q/DK7d2vWn
	AV5rgAFeRI96dZwQ0fhwIBy6555f5NBLfpHAjal1Y2T1dVZSKFLXGIBG9U8VNfGw9aNje4rJnrl
	vJlm65VwLKQ4ah9kiLSPjYAwfp2wtZpXHaToIjQzDM5m7LkYKAR2tSvibjWSeJiBNpfHVLHPM2/
	6+nPTaodnh8QTDvYkxRp0YKFEs+ARdNmXQRYDsMj70gcHIVxE6ihDJI9U11Eb4aCbiizWRw+0D8
	3w+cvG3uRfRkwvjO2OWaOktKj2GRG
X-Google-Smtp-Source: 
 AGHT+IELZUBLM5q9YYlt+lD2I0tWCOgW2YPV6e8Gm9HIS3wyPkKW8jVGcaajvDyvq1766HKI/b1QYg==
X-Received: by 2002:a17:907:7eaa:b0:ac3:45c6:a1ec with SMTP id
 a640c23a62f3a-ac738a841a3mr1407550166b.25.1743502269931;
        Tue, 01 Apr 2025 03:11:09 -0700 (PDT)
Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com.
 [35.204.239.8])
        by smtp.gmail.com with ESMTPSA id
 a640c23a62f3a-ac71967ffcdsm757406966b.140.2025.04.01.03.11.09
        (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
        Tue, 01 Apr 2025 03:11:09 -0700 (PDT)
From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
Date: Tue, 01 Apr 2025 11:11:02 +0100
Subject: [PATCH v5 1/2] dt-bindings: reset: syscon-reboot: add
 google,gs101-reboot
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: quoted-printable
Message-Id: <20250401-syscon-reboot-reset-mode-v5-1-5b9357442363@linaro.org>
References: <20250401-syscon-reboot-reset-mode-v5-0-5b9357442363@linaro.org>
In-Reply-To: <20250401-syscon-reboot-reset-mode-v5-0-5b9357442363@linaro.org>
To: Sebastian Reichel <sre@kernel.org>, Rob Herring <robh@kernel.org>,
 Krzysztof Kozlowski <krzk+dt@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>, Alim Akhtar <alim.akhtar@samsung.com>
Cc: Peter Griffin <peter.griffin@linaro.org>,
 Tudor Ambarus <tudor.ambarus@linaro.org>,
 Will McVicker <willmcvicker@google.com>, kernel-team@android.com,
 linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-samsung-soc@vger.kernel.org,
 =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
X-Mailer: b4 0.14.2

GS101 supports a couple different reset types via certain registers in
the SYSCON register map.

Add a compatible for it. When in effect, all register values and offsets
are implied, hence they shall not be specified in that case.

Signed-off-by: Andr=C3=A9 Draszik <andre.draszik@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 .../bindings/power/reset/syscon-reboot.yaml        | 42 +++++++++++++++---=
----
 1 file changed, 30 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.ya=
ml b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
index 19d3093e6cd2f7e39d94c56636dc202a4427ffc3..ccd5558700943ef56f5e1c86640=
0bcc21c0115f0 100644
--- a/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
+++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
@@ -21,7 +21,9 @@ description: |+
=20
 properties:
   compatible:
-    const: syscon-reboot
+    enum:
+      - syscon-reboot
+      - google,gs101-reboot
=20
   mask:
     $ref: /schemas/types.yaml#/definitions/uint32
@@ -49,12 +51,6 @@ properties:
   priority:
     default: 192
=20
-oneOf:
-  - required:
-      - offset
-  - required:
-      - reg
-
 required:
   - compatible
=20
@@ -63,12 +59,29 @@ additionalProperties: false
 allOf:
   - $ref: restart-handler.yaml#
   - if:
-      not:
-        required:
-          - mask
+      properties:
+        compatible:
+          contains:
+            const: google,gs101-reboot
     then:
-      required:
-        - value
+      properties:
+        mask: false
+        offset: false
+        reg: false
+        value: false
+
+    else:
+      if:
+        not:
+          required:
+            - mask
+      then:
+        required:
+          - value
+
+      oneOf:
+        - required: [offset]
+        - required: [reg]
=20
 examples:
   - |
@@ -78,3 +91,8 @@ examples:
         offset =3D <0x0>;
         mask =3D <0x1>;
     };
+
+  - |
+    reboot {
+        compatible =3D "google,gs101-reboot";
+    };

--=20
2.49.0.472.ge94155a9ec-goog

From nobody Wed May  7 05:15:22 2025
Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com
 [209.85.218.41])
	(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))
	(No client certificate requested)
	by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FFA81F03EF
	for <linux-kernel@vger.kernel.org>; Tue,  1 Apr 2025 10:11:12 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
 arc=none smtp.client-ip=209.85.218.41
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
	t=1743502274; cv=none;
 b=Ki/luX0qCx5WjJRDcF+Te1Tu626R9blgr5oYKPOhVGfCeWtWbHSsyp+hMFMvyOJa2ZACroKlTGS7sKwEqOQqmDZy7nQ2WJQnOYjtKlFG7RBGZisP6Bxmf1BFYE3oV0/B48RKpYf8svRhNsCmikR4BedcI63KjsplJNBRLtkk5vA=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
	s=arc-20240116; t=1743502274; c=relaxed/simple;
	bh=HRG8oyx+Mi+MU4biPMgGQvsmz+b2lSbgekhPGs2M778=;
	h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:
	 In-Reply-To:To:Cc;
 b=kp3g2XQlOSTprp//BOLEm4hNLMEKUxZttsVeBqpaqA0lnFdSft5inO32Q01GL26K3ani6rzOhDIeKLG2B3QuVtXqJaNVCJDqtna5C6WTveSo4bxcvBzCGu4Ft2QZUpFAWH3EQtQ0acoHY07e0XZSU2DWRvpsRIGI4W6jaLRMyg8=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
 dmarc=pass (p=none dis=none) header.from=linaro.org;
 spf=pass smtp.mailfrom=linaro.org;
 dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org
 header.b=yGVnOt1H; arc=none smtp.client-ip=209.85.218.41
Authentication-Results: smtp.subspace.kernel.org;
 dmarc=pass (p=none dis=none) header.from=linaro.org
Authentication-Results: smtp.subspace.kernel.org;
 spf=pass smtp.mailfrom=linaro.org
Authentication-Results: smtp.subspace.kernel.org;
	dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org
 header.b="yGVnOt1H"
Received: by mail-ej1-f41.google.com with SMTP id
 a640c23a62f3a-ac2a089fbbdso959626666b.1
        for <linux-kernel@vger.kernel.org>;
 Tue, 01 Apr 2025 03:11:12 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=linaro.org; s=google; t=1743502271; x=1744107071;
 darn=vger.kernel.org;
        h=cc:to:in-reply-to:references:message-id:content-transfer-encoding
         :mime-version:subject:date:from:from:to:cc:subject:date:message-id
         :reply-to;
        bh=tSsT7QLwFrGtJXgYzLTDttFLB1HtTy9nHcX9oWhHWK8=;
        b=yGVnOt1HGOcMEujFQdJiNC7MZmS3VlF5OT05LEG6wZchwxsIvyHnPGqdQATkHzKivs
         oNHjxkwo42l1kJFmf7ZNqAFCNqYPYlDOpNhwYEhZ1l9TWrirf6xD3O3Y+wNwV6TNP9iM
         Hr2hDTvMVxIWDKSHirh4+OXFSORBgQYmPtCcccOKPtSBz0YBvA6U2iG3HaxqpapdPO50
         sRlxdrYySX+yYDOZmJpdIioD8Uf52353I8Shq31ZEZd/gpl7MGXX8CAx0k1oHaW63uQr
         kQorHGGGLK0d89xzSxdorwrmeNKQqs0y6OBAqo29Vyy60E1yJBnbbrgvVpjTGidisH7a
         gfhQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=1e100.net; s=20230601; t=1743502271; x=1744107071;
        h=cc:to:in-reply-to:references:message-id:content-transfer-encoding
         :mime-version:subject:date:from:x-gm-message-state:from:to:cc
         :subject:date:message-id:reply-to;
        bh=tSsT7QLwFrGtJXgYzLTDttFLB1HtTy9nHcX9oWhHWK8=;
        b=L9tStHQ0gELZGfkhHEjn2qDagJqi6lj+lpAn5q86SfN5IAyYmz5feJ+xMRsxx7GNzG
         Sg91yaAnPjIsOgk5fmiEjQ3IRLF+kQAjL9Ps9dhfnGBI5thySwNZ6LaRalLULhihJQsV
         726PebEOsdyss0lNOFbOHpiW4hMebCQNMGjNaIaAvkAp5z0DWdtLIIN9L3EvawEzSwdh
         LHdjptpiiII3hs9Ics46DU4aR7M4HtguDyzFMqFWwJeILB4eiri3yEVmhFqafQFIxLb/
         TTnewiFhHMjIbr2gwSMtkzuKpPBKUZ6/11FgfH/zuSCRMO6yttSOoK3GojyVMJO53bZf
         8v+Q==
X-Forwarded-Encrypted: i=1;
 AJvYcCWL0iXchq+NNEjJ1dpXactg6o7fj2e5hWpOgFLosI5bWg0aMRYNFG6zsWsmAK/i88DozzptFYZUd4GMXZQ=@vger.kernel.org
X-Gm-Message-State: AOJu0YxSmj+/0mdCs0tmxKm/arQXsVxNyeE+h2SSZ8hLDZPjeF2LwLT6
	xd1uHdOpF8eaaCggWC+anIosdaq2Ca8+Tjh3wT26Nf8EzqGjzNcJ9HmnGomoWlM=
X-Gm-Gg: ASbGnctPdWyA/dBMO4f6vC0Z7ZWQGmeZhNdsomQVGRGLp8I/Q8bF3toBYA9hfBuWaBD
	CbM8YF2N2ylwdPkMRzNtktTkpT+JML47M83JjwHf4paQYK2byXKe536Sxx2dAy61hJh8DEJ4bh7
	JIAJMNrlUYpX9pITeYjx1NME+TkP7Lr5+FoNl6EKx2lt8iyScrKx3S13pWsNa2cKQKVLNxFUYy0
	tAoARXM+siXHvnKjz+rtbKhKreaUQ6BrroTktd6F6p+jZzCEjftVeeZ0NYwR/s9wOKnraHJ9NGA
	CKS0yHLNv925BQ2Xv/3MCH/bVWB83Fd+j8egdx5tWQtdDYXsHBNmlwnP0um0M1KqAo9TSUwC9A2
	MpmhkrtBbk7TyOIkY4+iCbvoKpKwO
X-Google-Smtp-Source: 
 AGHT+IGNz7sYkiZJ5SyCXOSh3R3E7uqsbcgG7MH73jgfKQy0aOMK7a6G6QNeK4q3SoREpDx6w1RXWQ==
X-Received: by 2002:a17:907:9482:b0:ac1:e45f:9c71 with SMTP id
 a640c23a62f3a-ac73670d581mr1256026066b.1.1743502270478;
        Tue, 01 Apr 2025 03:11:10 -0700 (PDT)
Received: from puffmais.c.googlers.com (8.239.204.35.bc.googleusercontent.com.
 [35.204.239.8])
        by smtp.gmail.com with ESMTPSA id
 a640c23a62f3a-ac71967ffcdsm757406966b.140.2025.04.01.03.11.10
        (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
        Tue, 01 Apr 2025 03:11:10 -0700 (PDT)
From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
Date: Tue, 01 Apr 2025 11:11:03 +0100
Subject: [PATCH v5 2/2] power: reset: syscon-reboot: add gs101-specific
 reset
Precedence: bulk
X-Mailing-List: linux-kernel@vger.kernel.org
List-Id: <linux-kernel.vger.kernel.org>
List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: quoted-printable
Message-Id: <20250401-syscon-reboot-reset-mode-v5-2-5b9357442363@linaro.org>
References: <20250401-syscon-reboot-reset-mode-v5-0-5b9357442363@linaro.org>
In-Reply-To: <20250401-syscon-reboot-reset-mode-v5-0-5b9357442363@linaro.org>
To: Sebastian Reichel <sre@kernel.org>, Rob Herring <robh@kernel.org>,
 Krzysztof Kozlowski <krzk+dt@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>, Alim Akhtar <alim.akhtar@samsung.com>
Cc: Peter Griffin <peter.griffin@linaro.org>,
 Tudor Ambarus <tudor.ambarus@linaro.org>,
 Will McVicker <willmcvicker@google.com>, kernel-team@android.com,
 linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 linux-samsung-soc@vger.kernel.org,
 =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
X-Mailer: b4 0.14.2

Linux supports a couple different reset modes, but this driver here
doesn't distinguish between them and issues the same syscon register
write irrespective of the reset mode requested by the kernel.

Since DTs should not encode register writes (see e.g. [1]), update this
driver to support different reset modes based on DT compatible match.

At the same time, add support for Google GS101, which does support
cold, hard, warm, and soft.

As an example why this is useful, other than properly supporting the
Linux reboot=3D kernel command line option or sysfs entry, this change
allows gs101-platforms to default to a more secure cold-reset, but also
to warm-reset in case RAM contents needs to be retained across the
reset.

Link: https://lore.kernel.org/all/20250227132644.GA1924628-robh@kernel.org/=
 [1]
Signed-off-by: Andr=C3=A9 Draszik <andre.draszik@linaro.org>
---
 drivers/power/reset/syscon-reboot.c | 98 +++++++++++++++++++++++++++++----=
----
 1 file changed, 77 insertions(+), 21 deletions(-)

diff --git a/drivers/power/reset/syscon-reboot.c b/drivers/power/reset/sysc=
on-reboot.c
index d623d77e657e4c233d8ae88bb099bee13c48a9ef..2e2cf5f62d733c7c07110f30525=
83607e25afd5d 100644
--- a/drivers/power/reset/syscon-reboot.c
+++ b/drivers/power/reset/syscon-reboot.c
@@ -14,11 +14,24 @@
 #include <linux/reboot.h>
 #include <linux/regmap.h>
=20
-struct syscon_reboot_context {
-	struct regmap *map;
+struct reboot_mode_bits {
 	u32 offset;
-	u32 value;
 	u32 mask;
+	u32 value;
+	bool valid;
+};
+
+struct reboot_data {
+	struct reboot_mode_bits mode_bits[REBOOT_SOFT + 1];
+	struct reboot_mode_bits catchall;
+};
+
+struct syscon_reboot_context {
+	struct regmap *map;
+
+	const struct reboot_data *rd; /* from of match data, if any */
+	struct reboot_mode_bits catchall; /* from DT */
+
 	struct notifier_block restart_handler;
 };
=20
@@ -28,9 +41,21 @@ static int syscon_restart_handle(struct notifier_block *=
this,
 	struct syscon_reboot_context *ctx =3D
 			container_of(this, struct syscon_reboot_context,
 					restart_handler);
+	const struct reboot_mode_bits *mode_bits;
+
+	if (ctx->rd) {
+		if (mode < ARRAY_SIZE(ctx->rd->mode_bits) &&
+		    ctx->rd->mode_bits[mode].valid)
+			mode_bits =3D &ctx->rd->mode_bits[mode];
+		else
+			mode_bits =3D &ctx->rd->catchall;
+	} else {
+		mode_bits =3D &ctx->catchall;
+	}
=20
 	/* Issue the reboot */
-	regmap_update_bits(ctx->map, ctx->offset, ctx->mask, ctx->value);
+	regmap_update_bits(ctx->map, mode_bits->offset, mode_bits->mask,
+			   mode_bits->value);
=20
 	mdelay(1000);
=20
@@ -42,7 +67,6 @@ static int syscon_reboot_probe(struct platform_device *pd=
ev)
 {
 	struct syscon_reboot_context *ctx;
 	struct device *dev =3D &pdev->dev;
-	int mask_err, value_err;
 	int priority;
 	int err;
=20
@@ -60,24 +84,33 @@ static int syscon_reboot_probe(struct platform_device *=
pdev)
 	if (of_property_read_s32(pdev->dev.of_node, "priority", &priority))
 		priority =3D 192;
=20
-	if (of_property_read_u32(pdev->dev.of_node, "offset", &ctx->offset))
-		if (of_property_read_u32(pdev->dev.of_node, "reg", &ctx->offset))
-			return -EINVAL;
+	ctx->rd =3D of_device_get_match_data(dev);
+	if (!ctx->rd) {
+		int mask_err, value_err;
=20
-	value_err =3D of_property_read_u32(pdev->dev.of_node, "value", &ctx->valu=
e);
-	mask_err =3D of_property_read_u32(pdev->dev.of_node, "mask", &ctx->mask);
-	if (value_err && mask_err) {
-		dev_err(dev, "unable to read 'value' and 'mask'");
-		return -EINVAL;
-	}
+		if (of_property_read_u32(pdev->dev.of_node, "offset",
+					 &ctx->catchall.offset) &&
+		    of_property_read_u32(pdev->dev.of_node, "reg",
+					 &ctx->catchall.offset))
+			return -EINVAL;
=20
-	if (value_err) {
-		/* support old binding */
-		ctx->value =3D ctx->mask;
-		ctx->mask =3D 0xFFFFFFFF;
-	} else if (mask_err) {
-		/* support value without mask*/
-		ctx->mask =3D 0xFFFFFFFF;
+		value_err =3D of_property_read_u32(pdev->dev.of_node, "value",
+						 &ctx->catchall.value);
+		mask_err =3D of_property_read_u32(pdev->dev.of_node, "mask",
+						&ctx->catchall.mask);
+		if (value_err && mask_err) {
+			dev_err(dev, "unable to read 'value' and 'mask'");
+			return -EINVAL;
+		}
+
+		if (value_err) {
+			/* support old binding */
+			ctx->catchall.value =3D ctx->catchall.mask;
+			ctx->catchall.mask =3D 0xFFFFFFFF;
+		} else if (mask_err) {
+			/* support value without mask */
+			ctx->catchall.mask =3D 0xFFFFFFFF;
+		}
 	}
=20
 	ctx->restart_handler.notifier_call =3D syscon_restart_handle;
@@ -89,7 +122,30 @@ static int syscon_reboot_probe(struct platform_device *=
pdev)
 	return err;
 }
=20
+static const struct reboot_data gs101_reboot_data =3D {
+	.mode_bits =3D {
+		[REBOOT_WARM] =3D {
+			.offset =3D 0x3a00, /* SYSTEM_CONFIGURATION */
+			.mask =3D 0x00000002, /* SWRESET_SYSTEM */
+			.value =3D 0x00000002,
+			.valid =3D true,
+		},
+		[REBOOT_SOFT] =3D {
+			.offset =3D 0x3a00, /* SYSTEM_CONFIGURATION */
+			.mask =3D 0x00000002, /* SWRESET_SYSTEM */
+			.value =3D 0x00000002,
+			.valid =3D true,
+		},
+	},
+	.catchall =3D {
+		.offset =3D 0x3e9c, /* PAD_CTRL_PWR_HOLD */
+		.mask =3D 0x00000100,
+		.value =3D 0x00000000,
+	},
+};
+
 static const struct of_device_id syscon_reboot_of_match[] =3D {
+	{ .compatible =3D "google,gs101-reboot", .data =3D &gs101_reboot_data  },
 	{ .compatible =3D "syscon-reboot" },
 	{}
 };

--=20
2.49.0.472.ge94155a9ec-goog