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AJvYcCX6IPkXEptnuzimTt8YQxRCLV5S1TDQIwllFCvwgfi7/fR3ilztUH/Odj/BxxPXsRlnNtg/RzZoJxhTnGQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz7XgkbZO0NVjuW9ApyL6gC7V4BXM4Mh5x6kl2WYuw2Y6vRrhos 7Fz5EyMC7/8aOTEWAv/C1gUYZyK5+lxlblIHYnfpB6Hi78CNfHOWawUtQedFQ1aCbCmHwWY7Ly8 qUsnd026loqCBoUWaonxlaETFPg== X-Google-Smtp-Source: AGHT+IGJF8B4sxZb6LHBqCORBrMjWxFGFtbVo3ixsesEJYQP3zIzMH571Rnw1V4KCZ3ejHSwrtmuRTWbQo8qDLDw2/U= X-Received: from pjbqi8.prod.google.com ([2002:a17:90b:2748:b0:301:2a0f:b03d]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3bc8:b0:305:2d68:8d91 with SMTP id 98e67ed59e1d1-3056094bca9mr1574788a91.28.1743462046748; Mon, 31 Mar 2025 16:00:46 -0700 (PDT) Date: Mon, 31 Mar 2025 16:00:24 -0700 In-Reply-To: <20250331230034.806124-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250331230034.806124-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250331230034.806124-3-willmcvicker@google.com> Subject: [PATCH v1 2/6] clocksource/drivers/exynos_mct: Don't register as a sched_clock on arm64 From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan , Krzysztof Kozlowski Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Donghoon Yu , Youngmin Nam Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When using the Exynos MCT as a sched_clock, accessing the timer value via the MCT register is extremely slow. To improve performance on Arm64 SoCs, use the Arm architected timer instead for timekeeping. Note, ARM32 SoCs don't have an architectured timer and therefore will continue to use the MCT timer. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/all/1400188079-21832-1-git-send-email-chirantan= @chromium.org/ Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7= 080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Will McVicker Reviewed-by:: Youngmin Nam --- drivers/clocksource/exynos_mct.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index da09f467a6bb..05c50f2f7a7e 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,12 @@ static struct clocksource mct_frc =3D { .resume =3D exynos4_frc_resume, }; =20 +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } =20 -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; =20 static cycles_t exynos4_read_current_timer(void) @@ -250,12 +250,13 @@ static int __init exynos4_clocksource_init(bool frc_s= hared) exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; exynos4_delay_timer.freq =3D clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif =20 if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); =20 - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); =20 return 0; } --=20 2.49.0.472.ge94155a9ec-goog