From nobody Fri Dec 19 21:30:41 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E62A215771 for ; Mon, 31 Mar 2025 23:00:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462046; cv=none; b=Drmm/nmHuhtEU7tjZaKZPqW/tuuxYx3aqTkJVSZyds9zJcsyE1NsD9DjD4DfhwFqv/x7iyOHGZsjbT5O9rc+AbXvP6bNbldsPfvvJfSfpH6tB84xRtL/JKOlm3i9yzhfzDTO83pM+tXurBN4+ydrPq3Naza/s0RaJpsIvE3DuQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462046; c=relaxed/simple; bh=Uu5UFR8h9rKzKbaED46JCrLLvQ/YDhWURODmFEk87y4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=oAe6FEEuNBwfOF8YBtfeyNIQXlLOvQzrd036boRPw6WF6JOfAz7Rz0TON1Ubh4V1tzJ0NKYC/L2wcM+dEALd1MjOJ54lRb/FgkDYzvG7JRBQRJCZ8icS+BY/jyLqmVUzcWg02s1rjLhmCi1y2PqLSVGij1fKhbyueBn6u4F5rOg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=ktdm0Xxj; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ktdm0Xxj" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-2ff68033070so8146834a91.2 for ; Mon, 31 Mar 2025 16:00:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1743462044; x=1744066844; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=2A1KKKyyzdpcSVMQiU3dhTgCCmATcVgptXdxBkHBo5A=; b=ktdm0Xxjp2YKHoQi9Gid4FqV1MiNaEfq3bVf5nHAAq/lYxgMxMHTtTFqwk6/1CJA4W SLKMccWGh3vB28tLsq4+a5M9fgy4eLEa+PtSIuMNNtP+3klAnJ8enMiuVo9onr1CPxsO blEJETMl7nhuXnmvsI5aCd9hNDILShU1nGz/N89ZfS3gx6xFoJnDhyYJm582GJV/Yhfr GQtLtlGZ5kiy1+sxi0zt0ZWUHHDRUAT8t2D9vyGa70aYtx8VJPEI3pq2Eo64mf9dCwX4 M6+1nVGd8Ayzk3M/++1X14BxU+jEG7o1HsPIxOXsmOBkFvlFFyuCSkBuRYY6hpR799OW RE7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743462044; x=1744066844; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=2A1KKKyyzdpcSVMQiU3dhTgCCmATcVgptXdxBkHBo5A=; b=c9XRXLyZHVPEaFrVWcGC4bsmLFwhLhKUTtzt4N4Wd5XcifkQISuatSg1vVq/Lrajzh H6AulwGI3ywZ4f6ksoi3Mic0lnASHBk955jc65H5au5fYlsUeDhChYZ8qtcm/Pk2mHOx Y4koWyrbscGCB3+kGqWcmS33iMXhiQ5L0sJPtvPCPAnpFydOju/hlCeWYAEQvs5LNpJq CDqTs3BChtAzat/5H1UvTZjr33HHWanZZYjBNzGYYPe9rlAuZNld2IwvB7dObzA/128I +n8gQiCWraKD9+Vtwit8sbL3rOUlAM8fEuImZODgWTi+v8gXbqnRhWtEsCe/hfPSiKxV pqzQ== X-Forwarded-Encrypted: i=1; AJvYcCXFFFkd3YEHdjTXt6+6oy2NEdjFGw011SuC6ED0knsbAQ3kUv2DIYf3XW54V7V++3BxudfqzpFd7zRWTNM=@vger.kernel.org X-Gm-Message-State: AOJu0YxFMaXdrb+1ZWGKTzMDqiuWnXtbPzeWJwT68SnHFn6hoootDT05 PHxgnxXdo6r4qV7irEcYPG48QakjUEOEFUEJM5LnLMEnYzTtnjopQlCbe146/jdSlB2JQQ4IXU8 FLRADc2rYsL2PGVjplC7KqNNAIQ== X-Google-Smtp-Source: AGHT+IG/ebJE2gKC/wqWBycsTxmqQFxHKcT+hLYLzDS5AFcHBpCYSXiF3vCmtkgKMTAKak4Gunic/DECRCqZWeNK0w8= X-Received: from pjbso14.prod.google.com ([2002:a17:90b:1f8e:b0:2ff:84e6:b2bd]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:e187:b0:2fe:a8b1:7d8 with SMTP id 98e67ed59e1d1-30560949dc0mr1232407a91.25.1743462044603; Mon, 31 Mar 2025 16:00:44 -0700 (PDT) Date: Mon, 31 Mar 2025 16:00:23 -0700 In-Reply-To: <20250331230034.806124-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250331230034.806124-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250331230034.806124-2-willmcvicker@google.com> Subject: [PATCH v1 1/6] of/irq: Export of_irq_count for modules From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Need to export `of_irq_count` in preparation for modularizing the Exynos MCT driver which uses this API for setting up the timer IRQs. Signed-off-by: Will McVicker Acked-by: Rob Herring (Arm) --- drivers/of/irq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index f8ad79b9b1c9..5adda1dac3cf 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -519,6 +519,7 @@ int of_irq_count(struct device_node *dev) =20 return nr; } +EXPORT_SYMBOL_GPL(of_irq_count); =20 /** * of_irq_to_resource_table - Fill in resource table with node's IRQ info --=20 2.49.0.472.ge94155a9ec-goog From nobody Fri Dec 19 21:30:41 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FC8C21CFF6 for ; Mon, 31 Mar 2025 23:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462049; cv=none; b=c0LvgsCiiXWsYkWEXVAkYUi0SpXs00Tky9VjbQctMVHfglN2tFayiz8EAj8AO+9KM5fgcbubmlySxhArRdbb4j98Q3cQUYUFZrYJSZ8jw3IIpyOrLdmudm6//Ck7qjaNn9xWrdOAMr/UZOtl3IfamxyFtLwyWhzz5wgagRF92UI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462049; c=relaxed/simple; bh=wY7+t4WrhnKpBLOfnJZyc9U97jJxjRqmIAP9fR9lAG4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=jnC8TM/XAg6tq6iBRUdNow9MUkdHvn6su/0dMHOg0Ztxt8t0txS6NwnCBVd7h9O4Fz1mgncLRrVS2u4hFhOgPY4Aa20vEu3oN3JKusfgR9vjlsr5j1l3AGHLLS642BIyIt+1o8Nzaa+eTJI3q5sSfIfo/Vd1w+jT/EQJihK8e/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=TMTU89ds; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="TMTU89ds" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-2ff6aaa18e8so8572372a91.1 for ; Mon, 31 Mar 2025 16:00:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1743462047; x=1744066847; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=rNxanwBhZtQZDwmjxM/W4Nk49HxAQJthjw2/nXfZ67g=; b=TMTU89dssJH4scHpaZuMNnTioJUQzdhLxS9C/zdUxUjCFT5/leU3IOatJv7I3KIQDq 4qsKKxTo9HtycvMw/3RzbJkO9f/Wl+stQOgv2VOaRw7HQy5KgfqPeI/pTq/A08MTUxti 77K8y2iRnLDrxfIBqPfbuUnGKS7AtfRDW4ehbq4kA1apaerKNQKhHW2Bmpayai4SFNMu 9PunSGEVLnhjsbL2WX9P8gky6jUnVfhXMxIqcOkcJG3Bwdor3KrCrYvBwPCFvu33r/TQ z4YqfiBJ0ncTLy4ou3Gn3P1QG3AfYfMBTDDzNQloh6c1qSgNHr/kGYN1NNRyxciUfWrw PtWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743462047; x=1744066847; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rNxanwBhZtQZDwmjxM/W4Nk49HxAQJthjw2/nXfZ67g=; b=wF1kWZj6gDUNlHCCi5UvvNmrDV8Au35ANTd2MBG7CN0+QJ+ANIWEFZX7LDTs11fnoO MNuohFxob/Sj9bx2G/g0u+Wv9Owr5R3BJdIPbSRXfst3khanq8ivgmKyuTclLpORMS8e jDiYWD3l5Al27zTZ80C9SRUANuYnkT1gQF+rwAi29p9S+DAF02AI5gNRDAT8D0KF8/GE nwnjukRkBqzCBlWvtXHNmD3SBrVO6ODPx3pMmbrwP+3+tXRSzTCiVPNr/7kN04WpTEx+ OUp6TKkMmr4AjJd42VrMxyt6WprVli9wrmDL7pi39Ymr2XnyFWZdJDIVy0VE7fommt+e DnOQ== X-Forwarded-Encrypted: i=1; AJvYcCX6IPkXEptnuzimTt8YQxRCLV5S1TDQIwllFCvwgfi7/fR3ilztUH/Odj/BxxPXsRlnNtg/RzZoJxhTnGQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yz7XgkbZO0NVjuW9ApyL6gC7V4BXM4Mh5x6kl2WYuw2Y6vRrhos 7Fz5EyMC7/8aOTEWAv/C1gUYZyK5+lxlblIHYnfpB6Hi78CNfHOWawUtQedFQ1aCbCmHwWY7Ly8 qUsnd026loqCBoUWaonxlaETFPg== X-Google-Smtp-Source: AGHT+IGJF8B4sxZb6LHBqCORBrMjWxFGFtbVo3ixsesEJYQP3zIzMH571Rnw1V4KCZ3ejHSwrtmuRTWbQo8qDLDw2/U= X-Received: from pjbqi8.prod.google.com ([2002:a17:90b:2748:b0:301:2a0f:b03d]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3bc8:b0:305:2d68:8d91 with SMTP id 98e67ed59e1d1-3056094bca9mr1574788a91.28.1743462046748; Mon, 31 Mar 2025 16:00:46 -0700 (PDT) Date: Mon, 31 Mar 2025 16:00:24 -0700 In-Reply-To: <20250331230034.806124-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250331230034.806124-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250331230034.806124-3-willmcvicker@google.com> Subject: [PATCH v1 2/6] clocksource/drivers/exynos_mct: Don't register as a sched_clock on arm64 From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan , Krzysztof Kozlowski Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Donghoon Yu , Youngmin Nam Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When using the Exynos MCT as a sched_clock, accessing the timer value via the MCT register is extremely slow. To improve performance on Arm64 SoCs, use the Arm architected timer instead for timekeeping. Note, ARM32 SoCs don't have an architectured timer and therefore will continue to use the MCT timer. Detailed discussion on this topic can be found at [1]. [1] https://lore.kernel.org/all/1400188079-21832-1-git-send-email-chirantan= @chromium.org/ Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam [Original commit from https://android.googlesource.com/kernel/gs/+/630817f7= 080e92c5e0216095ff52f6eb8dd00727 Signed-off-by: Will McVicker Reviewed-by:: Youngmin Nam --- drivers/clocksource/exynos_mct.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index da09f467a6bb..05c50f2f7a7e 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -219,12 +219,12 @@ static struct clocksource mct_frc =3D { .resume =3D exynos4_frc_resume, }; =20 +#if defined(CONFIG_ARM) static u64 notrace exynos4_read_sched_clock(void) { return exynos4_read_count_32(); } =20 -#if defined(CONFIG_ARM) static struct delay_timer exynos4_delay_timer; =20 static cycles_t exynos4_read_current_timer(void) @@ -250,12 +250,13 @@ static int __init exynos4_clocksource_init(bool frc_s= hared) exynos4_delay_timer.read_current_timer =3D &exynos4_read_current_timer; exynos4_delay_timer.freq =3D clk_rate; register_current_timer_delay(&exynos4_delay_timer); + + sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); #endif =20 if (clocksource_register_hz(&mct_frc, clk_rate)) panic("%s: can't register clocksource\n", mct_frc.name); =20 - sched_clock_register(exynos4_read_sched_clock, 32, clk_rate); =20 return 0; } --=20 2.49.0.472.ge94155a9ec-goog From nobody Fri Dec 19 21:30:41 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A9321D599 for ; Mon, 31 Mar 2025 23:00:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462050; cv=none; b=p80DquiR4OpMlPKP64ZXUPjiT4Gj3tMIZH84V9r9PDrJtPOiSLY0ZIEbaDHILSuQE8fu2aLDxw6MKyUgNH8Uz+onM3TIYS0NxbA/XZcAydY1jjXQUUkjOIJCDavth4LvBj0h3ir2WM8sgDvvGXSMk5Vno+1Nx+IrjkXk5zSaHgk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462050; c=relaxed/simple; bh=nZrzVWvi3ekw8G6oETZmBhKkYjcASs/pkTWr9Wls2ps=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=nMWejmmu8QJuQmUg3RxlT+ujlG+D3o7qdRsEGAhXG+CYotRdxMcDmRv4TtZss1uapOdD07qFdgJyOHSShhAK4UITP11u7ruXeDNVwWozoOqkvBTLER/Hrb+I2n8L6bPnZQ2tqVsyZkHNuHDBztUWOeUX79NmVeSsW/4h7q0btDE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=JkdZvR1E; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="JkdZvR1E" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2ff69646218so14833650a91.3 for ; Mon, 31 Mar 2025 16:00:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1743462049; x=1744066849; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=eYIAFf/wPB1FgKJfqKNRuXGM4xXRDDSYrMtDo5kebno=; b=JkdZvR1E7UHprJW3SOXV8NaTDVIaPLgtc2TGGCMAOhaCi3ViPO4j1hQVQsFTjUaWsA 9OBpuRFOzQSW3MBrrLdy7zh+xYorjC3kardDzJn3DO72ESOSArs/EjAB14Dy/fNw0toc 8R1X+xSChMwtXu/do3ctlEE1Eezi2tI9SWgJ1aknAsaL5rInFreOGsL7usB6ir5dewm+ kHGixtA4mF3bQu5lLvgXxipxPuV8sb7gVTN0Ow990vbl3IRJqs7zscFa7WEWDhLRVOYj hV/7wd/Ihn6l8tURGfX1H53OFWeuD0+4DLyRkJkkxkQ3MFVHRe20FtPrmP06LnNSipqP x70A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743462049; x=1744066849; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=eYIAFf/wPB1FgKJfqKNRuXGM4xXRDDSYrMtDo5kebno=; b=QrXFGu9LEbO9f64BmP1+ST6WwrGSBNfc/mQTmePiAQ6B5JJyfGYZExA8D83osw6ev9 khTU325LQrWT8cdmnztwZ5b0V0MF7vmHdSeVsnj6wUGA6Uj8ivcVFXX5r3/qKfIfWy3N gLOM3D4QBzIRT/UhY8I4aJ0X81GWZ4FAnejfp2OL+EeLEgaOH7kRNw4dpi4y2uF2Uvg3 jdl4ZximtbbML5Dr4UYq4pyqeSSCFYFsL3osegoffTgX19xhYTV/pRipLBKzrnHZtzKT U9xHrBt4HHveOEnGiDeZj7XFVsqJ1O9zBWi6c9KG8Ici0/iYT0wu6Bl3yh/mGlaDg19L EgvA== X-Forwarded-Encrypted: i=1; AJvYcCXAfwRwqoMMgrt64qcqO0bzU6lLtD/Kxrpzez1xkLm/gX7TK2ZEUNZBTDuptTl12NanoqT5D+2C9S1htgE=@vger.kernel.org X-Gm-Message-State: AOJu0YywHJxl36x0mPxD1cimu+Ffcv8a8GWtorEdAMWTYCMUUBteyYyv cDXc3Fwochch6ajIWpECLJsOgIB7MToRcFIo0GINkzNhW7zCCaXGv85PBHEPWiw0evzpvhctzlv q1fHN/uW12QrOwEb1f1UTwABfVQ== X-Google-Smtp-Source: AGHT+IFpiB1mL5vyi3i3SJZAHaJn7lRrJRhzSesvvlRpke5S6KVBbYcslhy5s8ASZECHhLaZs8DNDJw+s18hm0Fszqw= X-Received: from pjcc4.prod.google.com ([2002:a17:90b:5744:b0:2f2:e97a:e77f]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1644:b0:2ff:6aa6:47a3 with SMTP id 98e67ed59e1d1-30532164b69mr14496424a91.25.1743462048717; Mon, 31 Mar 2025 16:00:48 -0700 (PDT) Date: Mon, 31 Mar 2025 16:00:25 -0700 In-Reply-To: <20250331230034.806124-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250331230034.806124-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250331230034.806124-4-willmcvicker@google.com> Subject: [PATCH v1 3/6] clocksource/drivers/exynos_mct: Set local timer interrupts as percpu From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan , Krzysztof Kozlowski Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Hosung Kim Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hosung Kim The MCT local timers can be used as a per-cpu event timer. To prevent the timer interrupts from migrating to other CPUs, set the flag IRQF_PERCPU. Signed-off-by: Hosung Kim [Original commit from https://android.googlesource.com/kernel/gs/+/03267fad= 19f093bac979ca78309483e9eb3a8d16] Signed-off-by: Will McVicker --- drivers/clocksource/exynos_mct.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 05c50f2f7a7e..21ded37137d7 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -590,7 +590,8 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, irq_set_status_flags(mct_irq, IRQ_NOAUTOEN); if (request_irq(mct_irq, exynos4_mct_tick_isr, - IRQF_TIMER | IRQF_NOBALANCING, + IRQF_TIMER | IRQF_NOBALANCING | + IRQF_PERCPU, pcpu_mevt->name, pcpu_mevt)) { pr_err("exynos-mct: cannot register IRQ (cpu%d)\n", cpu); --=20 2.49.0.472.ge94155a9ec-goog From nobody Fri Dec 19 21:30:41 2025 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C2F421E08D for ; Mon, 31 Mar 2025 23:00:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462053; cv=none; b=fviWhxKSgXOuxZIw0ECddrI9SdAxGchDgVJQOLL/PLLanutEzy+JiNdMfGQSEFi7N90Qz0xMBWt7SJcKwlIQZ8MGqAmqo1z46/QJ3kNI+ulALu+4jkgc9pCPpZUaitv12d/FI7IiaImSNHSy6deGqpTFhD1gJxpWobxFgaD+mCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462053; c=relaxed/simple; bh=KGOLMUoqhgT8o6lRGzM2BT8QYWSv9CekKOeXvgxXs90=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=qxRwC30rj9onoHSnk+D/LA8kkGX9tiHKPpOIU5XAuj8PqMBO+m+aAIiHa1wX5XExaBjALsoEBDT77ovzsBlwQMh66WE8eY3eBzKHv7e0zxZPU4J66dOmqtBpYfKAkRZXabOWX8gQzr339pvx2Q1BcS4QEQdayCRmWO2UIr0kpeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=wYQMkyZy; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="wYQMkyZy" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-2241ae15dcbso115799155ad.0 for ; Mon, 31 Mar 2025 16:00:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1743462051; x=1744066851; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=5wAloBg1GSJoUoSs1Fe6e5szwOsXLtBgN31oDTUHQ8I=; b=wYQMkyZy8N9nZOYzO6KxRqJQvrUmw/4qH1j5bWRqEnMG1kDYwCOC60d/rny21PuK8P yYws+zq6B7QuxPCVvxx7lKf8U4s/kEKM25fVsC6JE8wCTDYn8LDBvzgAm6WePaVaduDB pPg0qT9JZrQnK7BJoI3+GVrRInOm0pz8PD2ykJOPFDeduX3ncidrgARhyftvTHT+dokQ oApg/Ei4yUsY3Adods0S0GBc/cfpGnZMsESchzBUHv8VZQB4QVRlNxlDRR7KCHuPYPuW KBS2D1QrOsF0FZHn2UoZQAS4lKGezNQWLpytH5s0d9j2msJkqa1WkThupR5Wz7D1121X 9GzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743462051; x=1744066851; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5wAloBg1GSJoUoSs1Fe6e5szwOsXLtBgN31oDTUHQ8I=; b=bEcfoaTDJ/zT0OjVkbDU2BLXj2q2f23+QD8h3YLZQhdTtoXunARkoOlyPEGjemG10n dANOAbdisu56S4AyNSnSCVaH9dDbvyWsq5/g1QSVQLwLQJAJCJgfGg3NhwufpA+cmSCW tIYNvPw3JRnTILmIARFeml/fgw0SJp18B4yVeAeOFxWuftPswAt21uk+9WScvhWL/W4K FzNbmY1++ZJUt2G4axv2gg3ba8Khkux/SuONaaTxLDz6bg3E+f+en+/VryRlU6fAbG1G nS2wAAz7K/RUcdA03wXvT50a6N7y0sWnsib0XqJOoEWAAsKIuT1BJJ3LSCYS8fBsU0es fdsw== X-Forwarded-Encrypted: i=1; AJvYcCXGBx5/UGlt9kQ+qCwHj0F2Zt68K9vgQBZWr5MHt8yrSbjfTGAyX0y/MgFVeYoUgwkcK9uOrFwCM5IJRrA=@vger.kernel.org X-Gm-Message-State: AOJu0YxVSy4ZtNgDQxxrnmxRFcf/weYfzt/mCN6iw1Y7hS+xcjrgowVp cxf18lzbGOnLZRdStjCJt+O/AliF+Rr3eT4BD3nNH8vcOx6Mi9EPZ/NQ+wugnMuZ/0kjtZfNqBY STCZJe2gopiCePJ2C6BnGTqLhuQ== X-Google-Smtp-Source: AGHT+IFhkqYe7aFPYhXhB/uXFuJRx2APqvedOXzVTYhLwQ5pf0aEv93uw3ToHTM6Wa3C2QveIbk5Q7eGKFiWITWBEiY= X-Received: from pfbit9.prod.google.com ([2002:a05:6a00:4589:b0:736:5b36:db8f]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:4fd3:b0:736:53f2:87bc with SMTP id d2e1a72fcca58-739803994b1mr16712693b3a.13.1743462050772; Mon, 31 Mar 2025 16:00:50 -0700 (PDT) Date: Mon, 31 Mar 2025 16:00:26 -0700 In-Reply-To: <20250331230034.806124-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250331230034.806124-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250331230034.806124-5-willmcvicker@google.com> Subject: [PATCH v1 4/6] arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Will Deacon Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Will Deacon In preparation for switching to the architected timer as the primary clockevents device, mark the cpuidle nodes with the 'local-timer-stop' property to indicate that an alternative clockevents device must be used for waking up from the "c2" idle state. Signed-off-by: Will Deacon [Original commit from https://android.googlesource.com/kernel/gs/+/a896fd98= 638047989513d05556faebd28a62b27c] Signed-off-by: Will McVicker --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 3de3a758f113..fd0badf24e6f 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -155,6 +155,7 @@ ananke_cpu_sleep: cpu-ananke-sleep { idle-state-name =3D "c2"; compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x0010000>; + local-timer-stop; entry-latency-us =3D <70>; exit-latency-us =3D <160>; min-residency-us =3D <2000>; @@ -164,6 +165,7 @@ enyo_cpu_sleep: cpu-enyo-sleep { idle-state-name =3D "c2"; compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x0010000>; + local-timer-stop; entry-latency-us =3D <150>; exit-latency-us =3D <190>; min-residency-us =3D <2500>; @@ -173,6 +175,7 @@ hera_cpu_sleep: cpu-hera-sleep { idle-state-name =3D "c2"; compatible =3D "arm,idle-state"; arm,psci-suspend-param =3D <0x0010000>; + local-timer-stop; entry-latency-us =3D <235>; exit-latency-us =3D <220>; min-residency-us =3D <3500>; --=20 2.49.0.472.ge94155a9ec-goog From nobody Fri Dec 19 21:30:41 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80CC122068B for ; Mon, 31 Mar 2025 23:00:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462056; cv=none; b=V7UDKQ2BQ4n93i5HFCxtR2BtX+uDBTV+fae4ZNQ27ySaCK2dD1WISeTEgzL3+c+/6/AbsU29m9t33kmWNE7XYOnaheo0yaWascEWWLDuBC2Bpupznw5ATrZqLV7aKaHwoDxiIp2AaxtJ03RRmr2auFPlOrKnW0yxsY84ORW/kfA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462056; c=relaxed/simple; bh=ne78zXxTrl/nYlmfq+K5BGZIbA2NVuWMAyqVxlQu7dM=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=fz+/qP28XistFWEl4eODgM9zONQt5i41IVho9e/caoAHNO1dyj7ROZgFbRUZB7KzAg+0Nv1jVRslT2cnQE4u7KfUbwTNuCfz6ZcSvwgyCkIqY6Ti48I1qgiOkTXzrKO0zUpAQuzEffiFBLMTMr++cJ+ZDXCFycJ1JKiVPBCdUro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Y5WDjYoc; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Y5WDjYoc" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2ff6943febeso7737471a91.0 for ; Mon, 31 Mar 2025 16:00:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1743462053; x=1744066853; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=ulmUmxoKn2frrsYltohW0CKthat5ISQxrYAQM4kkNLU=; b=Y5WDjYocQCKQxFtEcvnjtD24XNmswdrFDEnQtl/Q8tyJjxKjY535amD2qZLEwdZMlx EU3sS++ppNwK1sMfIJLzraSs2qkWLsi0V6rqvIEtguUE2fob4A4Mvt5gewz8pq9n3eb+ xDHlAXhez0x7smWNYIwWEfZV/CqrxqOmSvaAERZetIVDs8qhqBVkS5kAhYJ7MqtOlOhW UCwpU8nt8NNEcQdiYVQUlzJXdveKU0dxOAQz6n4D752WbXgUD8ajcOLAPWb0H6ZDb6xY 3zZWE46F5ofvD0Wg9kWFQKsBfeIRZvpCEgKkfhyowLSRe72oAce5lroeV6ajVrAt3QFP GbgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743462053; x=1744066853; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ulmUmxoKn2frrsYltohW0CKthat5ISQxrYAQM4kkNLU=; b=v2275kwtEyDw2T2kNv8gGNxVJzpIPpa+JvfpcHb/610+oUQjJ3oef0aTbrCxFgDyQk eyeEpyh3Nc+ChUxsWdEs1Ebzh6SK3WWQuYiEJU/XkeKSLpM0TlyJFxji6nZ0fsWP7Xx2 NVt6oz+bGdd4TDwM8tJQi+a/osLZPs70ixJ2cutl/NsdIaGBLJO1t/DRFXnaQTqMyvsb lA0C5neq/qg/dJPa+1BOHQfnHwdLfax3+dd3/XCZOyJPqZnLE61EMz2o9sZOpZEmtFgb hkw9rkF+7/YCbHYgvREaxPbIFep/c+KrHAbkroPfr7x8Aj/9ZBNM4ClHRiqmW7odiWNH I6LA== X-Forwarded-Encrypted: i=1; AJvYcCVHbcTCqx9VXCccGEJmVimh6mjy7Wf9fWDEKbzrU6YEIP0BMrV0EhWt3sbatDSoNEzO8oAsVXGjfdiU9Fc=@vger.kernel.org X-Gm-Message-State: AOJu0YwC0HIcYaUCVGc85y0XNH7qxYHoUnLM9BukOjJykTTjKw9YBkiE 5qGi0nEAlLsZ1NI/MDbrLxNHxPJswUJ6IlT7Wd+tCIF1kHJfW08HjHR+UzmSDZj7ItO7f77VNA/ VIY/0q8Be4aIDPDJQe44wbVzOKw== X-Google-Smtp-Source: AGHT+IE5NyFQYus/tf1QYYAFIfVAMg9yb/cSsm8CoRrwBXhSWC0iBExikv4kLw7OwXIeyQY2hQdq59zsfug5q/X9xxE= X-Received: from pjbsb5.prod.google.com ([2002:a17:90b:50c5:b0:2ff:4ba2:f3a5]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1cc7:b0:2fa:1d9f:c80 with SMTP id 98e67ed59e1d1-3051c9752admr21092256a91.17.1743462053067; Mon, 31 Mar 2025 16:00:53 -0700 (PDT) Date: Mon, 31 Mar 2025 16:00:27 -0700 In-Reply-To: <20250331230034.806124-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250331230034.806124-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250331230034.806124-6-willmcvicker@google.com> Subject: [PATCH v1 5/6] clocksource/drivers/exynos_mct: Add module support From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan , Krzysztof Kozlowski Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, Donghoon Yu , Youngmin Nam Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Donghoon Yu On Arm64 platforms the Exynos MCT driver can be built as a module. On boot (and even after boot) the arch_timer is used as the clocksource and tick timer. Once the MCT driver is loaded, it can be used as the wakeup source for the arch_timer. Signed-off-by: Donghoon Yu Signed-off-by: Youngmin Nam [Original commit from https://android.googlesource.com/kernel/gs/+/8a52a828= 8ec7d88ff78f0b37480dbb0e9c65bbfd] Signed-off-by: Will McVicker --- drivers/clocksource/Kconfig | 3 +- drivers/clocksource/exynos_mct.c | 47 +++++++++++++++++++++++++++----- 2 files changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 487c85259967..e5d9d8383607 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -443,7 +443,8 @@ config ATMEL_TCB_CLKSRC Support for Timer Counter Blocks on Atmel SoCs. =20 config CLKSRC_EXYNOS_MCT - bool "Exynos multi core timer driver" if COMPILE_TEST + tristate "Exynos multi core timer driver" + default y if ARCH_EXYNOS depends on ARM || ARM64 depends on ARCH_ARTPEC || ARCH_EXYNOS || COMPILE_TEST help diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_= mct.c index 21ded37137d7..da4460d8a0ba 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -15,9 +15,11 @@ #include #include #include +#include #include #include #include +#include #include #include =20 @@ -235,7 +237,7 @@ static cycles_t exynos4_read_current_timer(void) } #endif =20 -static int __init exynos4_clocksource_init(bool frc_shared) +static int exynos4_clocksource_init(bool frc_shared) { /* * When the frc is shared, the main processor should have already @@ -507,7 +509,7 @@ static int exynos4_mct_dying_cpu(unsigned int cpu) return 0; } =20 -static int __init exynos4_timer_resources(struct device_node *np) +static int exynos4_timer_resources(struct device_node *np) { struct clk *mct_clk, *tick_clk; =20 @@ -535,7 +537,7 @@ static int __init exynos4_timer_resources(struct device= _node *np) * @local_idx: array mapping CPU numbers to local timer indices * @nr_local: size of @local_idx array */ -static int __init exynos4_timer_interrupts(struct device_node *np, +static int exynos4_timer_interrupts(struct device_node *np, unsigned int int_type, const u32 *local_idx, size_t nr_local) @@ -640,7 +642,7 @@ static int __init exynos4_timer_interrupts(struct devic= e_node *np, return err; } =20 -static int __init mct_init_dt(struct device_node *np, unsigned int int_typ= e) +static int mct_init_dt(struct device_node *np, unsigned int int_type) { bool frc_shared =3D of_property_read_bool(np, "samsung,frc-shared"); u32 local_idx[MCT_NR_LOCAL] =3D {0}; @@ -688,15 +690,46 @@ static int __init mct_init_dt(struct device_node *np,= unsigned int int_type) return exynos4_clockevent_init(); } =20 - -static int __init mct_init_spi(struct device_node *np) +static int mct_init_spi(struct device_node *np) { return mct_init_dt(np, MCT_INT_SPI); } =20 -static int __init mct_init_ppi(struct device_node *np) +static int mct_init_ppi(struct device_node *np) { return mct_init_dt(np, MCT_INT_PPI); } + +#ifdef MODULE +static int exynos4_mct_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + + if (of_machine_is_compatible("samsung,exynos4412-mct")) + return mct_init_ppi(np); + + return mct_init_spi(np); +} + +static const struct of_device_id exynos4_mct_match_table[] =3D { + { .compatible =3D "samsung,exynos4210-mct" }, + { .compatible =3D "samsung,exynos4412-mct" }, + {} +}; +MODULE_DEVICE_TABLE(of, exynos4_mct_match_table); + +static struct platform_driver exynos4_mct_driver =3D { + .probe =3D exynos4_mct_probe, + .driver =3D { + .name =3D "exynos-mct", + .of_match_table =3D exynos4_mct_match_table, + }, +}; +module_platform_driver(exynos4_mct_driver); +#else TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); +#endif + +MODULE_DESCRIPTION("Exynos Multi Core Timer Driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0.472.ge94155a9ec-goog From nobody Fri Dec 19 21:30:41 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 995C12206B8 for ; Mon, 31 Mar 2025 23:00:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462057; cv=none; b=LktRaFZvaPR2PsWEI4sodyAuqatJzFFzYK/WvrG0L6gXoROWFP96jRSIlrMOlPfYoMANNOJdEXKkQHidBa69Lwhb8nVvvaVn2MBIZ5Ag5BVF9gaT6qKFTVH4UFVjTUkTtPdSZ73T3mYTyD1uNfOr84wR1x3b9uyi1xkaW8Z/wGg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743462057; c=relaxed/simple; bh=BHqjnEz8Bqub0+5tOgaodvHpe7VxxoEtAWRFbgVwkX4=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=PsPL5Gn1d/UUQLFMOr/1Y/fRib5K1WlAsFtTVWRnGMFxyRem4znzdV2DyVyIPW3sC3Lw/ICNdZVgGg1fC4tZHbMXzFJWKMJqJTGJHSTawYXPXE/uWa9TbWhdJcK5kn68MdSs7H24ZAGxNXEm2qHDsXmMRFBeTBtYcU6AVIifw3Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=JVzwCa07; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--willmcvicker.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="JVzwCa07" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2ff7cf599beso9012273a91.0 for ; Mon, 31 Mar 2025 16:00:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1743462055; x=1744066855; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=vqQfU5MFNX+M9dMbS6b209zYYBr6gV4W0L8ERj/h45U=; b=JVzwCa07ULKllNkA4NAq28yzX29CDrNJkwpPA9OcKklGFxso2haopT1HH19HZvpRmo /hH+FHfWhfZfTiCidtD1MevbqeqeT/wcaeyYgEjLnz8dvh0d09SxtavLKghSlJJsOMn6 HXnyvbDbYdwFdmWBEGCxxuRm0C40YOQS7iPBU22lnAr8TXZJVaWO06h1zaIfQsmsH9ZF YntP58HfB2w3BNu4VCq8p5SsfaGGphjm5JMmaNIceW5tJY2LOf0+PpNRvJr9eSOdIeY6 p8gX2CHOgoP++F62MtJ4hypay1iG6pepMcquPI74iHTWOGdrpamhnsz8aU9Lv8wn1MWq MUNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743462055; x=1744066855; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=vqQfU5MFNX+M9dMbS6b209zYYBr6gV4W0L8ERj/h45U=; b=eTAxSxbC0QeW+8BGgPwEc/EfP4+wDzNF+IQQTv2NKxKb0HGHaWMYl1nKxdfquYLotV REHYnmRef9b+ZpSFjJFqCQvp3Nnr4yEO0SzyUJkVWdA1L/GH2Dy6w13i2FTFuavUr+7r 8N0uz9STWq44lA7FMrqLrAospK+sC3PhvbG1zNfGJBZid6VpFeBAaCU+t/7Nm0F+jLhP zVU/gcfMURiRYzvh1kJ1pD5NNZMB8rl430pMXUW6aQp/MH1eCWD2TDJGEF8RiXo5Nbw9 5GkkIWhaR3/6Nf/BQv5jAdfDDDwsWyFsgIsUyYRuuQougL3zdHNQlb1fesZckximqxKv EB6g== X-Forwarded-Encrypted: i=1; AJvYcCV9X/1Up7Eood8jTnBicJt2ht6apvieHwKG3YhzYxUIC77bT057GjdO5DELNZURqCdyQnenACZFbTNMUZs=@vger.kernel.org X-Gm-Message-State: AOJu0YzbWsoOOmrYP0chCw5sZZ80nJiXBp3rKTWw0P+UqD709Xl1KLC7 V8ylL8YhZZqWSsrK6zMCB/wWVlAPUgMcUVsulHRqvgJJPWUzSIVWPrFNvMqkrm2lhZ1YZ08qZIE UWT44AObX111L9IiWpM0uJHoxng== X-Google-Smtp-Source: AGHT+IEx4n4bxYc/YGt82JQ6y5gWLCjA7rtOL1EcSQ5FOyxHXLQUeEqlUnQfPzSQjxNpXS/pD1jk7mi3qLuRMiZ4+F4= X-Received: from pjbmj3.prod.google.com ([2002:a17:90b:3683:b0:305:2d68:2be6]) (user=willmcvicker job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3c06:b0:2fe:994d:613b with SMTP id 98e67ed59e1d1-3053215a3d8mr16944353a91.35.1743462055036; Mon, 31 Mar 2025 16:00:55 -0700 (PDT) Date: Mon, 31 Mar 2025 16:00:28 -0700 In-Reply-To: <20250331230034.806124-1-willmcvicker@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250331230034.806124-1-willmcvicker@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250331230034.806124-7-willmcvicker@google.com> Subject: [PATCH v1 6/6] arm64: exynos: Drop select CLKSRC_EXYNOS_MCT From: Will McVicker To: Catalin Marinas , Will Deacon , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Daniel Lezcano , Thomas Gleixner , Saravana Kannan Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since the Exynos MCT driver can be built as a module for some Arm64 SoCs like gs101, drop force-selecting it as a built-in driver by ARCH_EXYNOS and instead depend on `default y if ARCH_EXYNOS` to select it automatically. This allows platforms like Android to build the driver as a module if desired. Signed-off-by: Will McVicker --- arch/arm64/Kconfig.platforms | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8b76821f190f..325279193e2c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -109,7 +109,6 @@ config ARCH_BLAIZE config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG - select CLKSRC_EXYNOS_MCT select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select EXYNOS_PMU select PINCTRL --=20 2.49.0.472.ge94155a9ec-goog