From nobody Fri Dec 19 21:28:57 2025 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6693A1DE8A2; Mon, 31 Mar 2025 10:31:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743417114; cv=none; b=RL64vMAqeOxwDqUOGfUgaNbpcik2NXLTVeeEltrwovryJi4+gnmx/HvIebrOMaHqu7eRb5RnlV8Yoy25YQf3AOC76h47OoR/R2OXavYGBkKHQ6iERzwuzN5yQkRJ5YfTzAWq6iGtEMJNQ4jidcto1xSJywSqvkwnxkRpGOz4zis= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743417114; c=relaxed/simple; bh=5WNycKrzzUJ/vc5KSY4/uxMt8yevVuyNg9h182DqKoo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ragqtRD3Fw2+WYLt9n8qKjXnQR08xtOhGoz+eegDjcBJkC244l2he01GImtVYi86XuGo52uHtssMN0Jh88fSLr2bu4jzykNrFjyiKuBJ1hok5X+qnYk90R0AaI13Aq63hlnaAfuJB1qK/qaFK4GaOsB/XdxvYXsdxO71iV56ebY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=bLcVEj5r; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="bLcVEj5r" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 06DD31026C8AF; Mon, 31 Mar 2025 12:31:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1743417109; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=pvqw6982EGCfcMZjsBd3rEgWv+Hsc7YWNppWaSfoULI=; b=bLcVEj5rxdkwq1fctb6GdrTaHcFxNDwVmfq1yIVDWmLhAA+G/ZoMA6Zt8Sf3JzHLZ2c1l4 8YC5FFoAP80T2FC8i+WcJ6ColgiZDbDLzCurvDhTLmEFSPJ5sv6tHwxIVCNdHHtuiErlHt /dkTSJKDbJwwHEvoaZoHqagZVFBDgzvaSTrTurVfkJon2WonpbbAJD9dEF3iVcs+E4KdB8 iB8Ve6nBhN1P3a3og4JKx9//FVb+w9oqmORhYAQ3qOM7FxOV/rbM1XQyR0BkdtFzSUctWX vgNqNGDvR6x/8JdOQACVsIGZQoZAzSCwgc9uNJZ46seqcFaCbMUyLX7K+srXtQ== From: Lukasz Majewski To: Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Richard Cochran , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Lukasz Majewski Subject: [PATCH v3 1/4] dt-bindings: net: Add MTIP L2 switch description Date: Mon, 31 Mar 2025 12:31:13 +0200 Message-Id: <20250331103116.2223899-2-lukma@denx.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250331103116.2223899-1-lukma@denx.de> References: <20250331103116.2223899-1-lukma@denx.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" This patch provides description of the MTIP L2 switch available in some NXP's SOCs - e.g. imx287. Signed-off-by: Lukasz Majewski --- Changes for v2: - Rename the file to match exactly the compatible (nxp,imx287-mtip-switch) Changes for v3: - Remove '-' from const:'nxp,imx287-mtip-switch' - Use '^port@[12]+$' for port patternProperties - Drop status =3D "okay"; - Provide proper indentation for 'example' binding (replace 8 spaces with 4 spaces) - Remove smsc,disable-energy-detect; property - Remove interrupt-parent and interrupts properties as not required - Remove #address-cells and #size-cells from required properties check - remove description from reg: - Add $ref: ethernet-switch.yaml# --- .../bindings/net/nxp,imx287-mtip-switch.yaml | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/nxp,imx287-mtip-s= witch.yaml diff --git a/Documentation/devicetree/bindings/net/nxp,imx287-mtip-switch.y= aml b/Documentation/devicetree/bindings/net/nxp,imx287-mtip-switch.yaml new file mode 100644 index 000000000000..98eba3665f32 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nxp,imx287-mtip-switch.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nxp,imx287-mtip-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP SoC Ethernet Switch Controller (L2 MoreThanIP switch) + +maintainers: + - Lukasz Majewski + +description: + The 2-port switch ethernet subsystem provides ethernet packet (L2) + communication and can be configured as an ethernet switch. It provides t= he + reduced media independent interface (RMII), the management data input + output (MDIO) for physical layer device (PHY) management. + +$ref: ethernet-switch.yaml# + +properties: + compatible: + const: nxp,imx287-mtip-switch + + reg: + maxItems: 1 + + phy-supply: + description: + Regulator that powers Ethernet PHYs. + + clocks: + items: + - description: Register accessing clock + - description: Bus access clock + - description: Output clock for external device - e.g. PHY source cl= ock + - description: IEEE1588 timer clock + + clock-names: + items: + - const: ipg + - const: ahb + - const: enet_out + - const: ptp + + interrupts: + items: + - description: Switch interrupt + - description: ENET0 interrupt + - description: ENET1 interrupt + + pinctrl-names: true + + ethernet-ports: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + '^port@[12]+$': + type: object + description: MTIP L2 switch external ports + + $ref: ethernet-controller.yaml# + unevaluatedProperties: false + + properties: + reg: + items: + - enum: [1, 2] + description: MTIP L2 switch port number + + label: + description: Label associated with this port + + required: + - reg + - label + - phy-mode + - phy-handle + + mdio: + type: object + $ref: mdio.yaml# + unevaluatedProperties: false + description: + Specifies the mdio bus in the switch, used as a container for phy no= des. + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - mdio + - ethernet-ports + +additionalProperties: false + +examples: + - | + #include + switch@800f0000 { + compatible =3D "nxp,imx287-mtip-switch"; + reg =3D <0x800f0000 0x20000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mac0_pins_a>, <&mac1_pins_a>; + phy-supply =3D <®_fec_3v3>; + interrupts =3D <100>, <101>, <102>; + clocks =3D <&clks 57>, <&clks 57>, <&clks 64>, <&clks 35>; + clock-names =3D "ipg", "ahb", "enet_out", "ptp"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mtip_port1: port@1 { + reg =3D <1>; + label =3D "lan0"; + local-mac-address =3D [ 00 00 00 00 00 00 ]; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy0>; + }; + + mtip_port2: port@2 { + reg =3D <2>; + label =3D "lan1"; + local-mac-address =3D [ 00 00 00 00 00 00 ]; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy1>; + }; + }; + + mdio_sw: mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + reset-gpios =3D <&gpio2 13 0>; + reset-delay-us =3D <25000>; + reset-post-delay-us =3D <10000>; + + ethphy0: ethernet-phy@0 { + reg =3D <0>; + }; + + ethphy1: ethernet-phy@1 { + reg =3D <1>; + }; + }; + }; --=20 2.39.5