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[2a02:3100:ad73:6800::e63]) by smtp.googlemail.com with ESMTPSA id a640c23a62f3a-ac7196dd46asm364497866b.160.2025.03.29.11.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Mar 2025 11:59:24 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, jbrunet@baylibre.com, khilman@baylibre.com, neil.armstrong@linaro.org, christianshewitt@gmail.com, Martin Blumenstingl Subject: [PATCH 4/7] arm64: dts: amlogic: gxl: enable UART RX and TX pull up by default Date: Sat, 29 Mar 2025 19:58:52 +0100 Message-ID: <20250329185855.854186-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250329185855.854186-1-martin.blumenstingl@googlemail.com> References: <20250329185855.854186-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/d= ts/amlogic/meson-gxl.dtsi index 2dc2fdaecf9f..460c46cfad6a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -163,7 +163,7 @@ uart_ao_a_pins: uart_ao_a { mux { groups =3D "uart_tx_ao_a", "uart_rx_ao_a"; function =3D "uart_ao"; - bias-disable; + bias-pull-up; }; }; =20 @@ -180,7 +180,7 @@ uart_ao_b_pins: uart_ao_b { mux { groups =3D "uart_tx_ao_b", "uart_rx_ao_b"; function =3D "uart_ao_b"; - bias-disable; + bias-pull-up; }; }; =20 @@ -188,7 +188,7 @@ uart_ao_b_0_1_pins: uart_ao_b_0_1 { mux { groups =3D "uart_tx_ao_b_0", "uart_rx_ao_b_1"; function =3D "uart_ao_b"; - bias-disable; + bias-pull-up; }; }; =20 @@ -522,7 +522,7 @@ mux { groups =3D "uart_tx_a", "uart_rx_a"; function =3D "uart_a"; - bias-disable; + bias-pull-up; }; }; =20 @@ -540,7 +540,7 @@ mux { groups =3D "uart_tx_b", "uart_rx_b"; function =3D "uart_b"; - bias-disable; + bias-pull-up; }; }; =20 @@ -558,7 +558,7 @@ mux { groups =3D "uart_tx_c", "uart_rx_c"; function =3D "uart_c"; - bias-disable; + bias-pull-up; }; }; =20 --=20 2.49.0