From nobody Tue Oct 14 01:25:57 2025 Received: from out-174.mta0.migadu.com (out-174.mta0.migadu.com [91.218.175.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB6931C5F23 for ; Sat, 29 Mar 2025 11:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743248407; cv=none; b=YSF3Q7JZr0SGFxe7tpXW9wq8i2BYNHQfJswxfU6i3KsnC/rDdZSGTRCvHhRtke+voJVbpENNkY4PCqDAwzksp5hcKNp7Gcz6iLuTmp29hrkiz9LT8DDfyqkyaibyc+afvV/exXf9B07oSZdCLDmvcOOp28RG6qDM2l/BMA/VaXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743248407; c=relaxed/simple; bh=4ZeWdO9vWBQvCeusrKYzW1xKaowzbrUNRAEcKZOnMWo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WUC6/w27xpJSw596jyUWKeqzuId/FdC4DITJwPmUegPQDzfCHInLawByr9UTmFBThiN3L6ze02CrVw+fzqMyrAeNvXIXqFB5wglYMq0I4m2UsaSf4u3acvIHsFdBjH48pZR8BVOatTQxfFX3JDQ5KarYqSgyjC9X48d8OI9DJEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=bg7IBuNj; arc=none smtp.client-ip=91.218.175.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="bg7IBuNj" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1743248402; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+ZUmc0mq21gmsiUqtz6/4c/LeqvF+5GvQEyiqdwc40U=; b=bg7IBuNjl/kOFEjc6vu5s8/EsngGR/+XRlzlLEqwPI3BPh+CYPEYQ8RAwFk1Bflsn0jZ+m FtnISIz7vW6dESONrDjnBhajTDWpgKioalwSfVTcHuzrkORep0yPS2VJTt2nmdtGw2bZed q56zZQOmk3xVQqSNX5T64oMXpLHqfhg= From: Aradhya Bhatia To: Tomi Valkeinen , Dmitry Baryshkov , Laurent Pinchart , Andrzej Hajda , Neil Armstrong , Robert Foss , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Nishanth Menon , Vignesh Raghavendra , Devarsh Thakkar , Praneeth Bajjuri , Udit Kumar , Jayesh Choudhary , Alexander Sverdlin , Dominik Haller , DRI Development List , Linux Kernel List , Aradhya Bhatia , stable@vger.kernel.org Subject: [PATCH v11 05/14] drm/bridge: cdns-dsi: Wait for Clk and Data Lanes to be ready Date: Sat, 29 Mar 2025 17:09:16 +0530 Message-Id: <20250329113925.68204-6-aradhya.bhatia@linux.dev> In-Reply-To: <20250329113925.68204-1-aradhya.bhatia@linux.dev> References: <20250329113925.68204-1-aradhya.bhatia@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" From: Aradhya Bhatia Once the DSI Link and DSI Phy are initialized, the code needs to wait for Clk and Data Lanes to be ready, before continuing configuration. This is in accordance with the DSI Start-up procedure, found in the Technical Reference Manual of Texas Instrument's J721E SoC[0] which houses this DSI TX controller. If the previous bridge (or crtc/encoder) are configured pre-maturely, the input signal FIFO gets corrupt. This introduces a color-shift on the display. Allow the driver to wait for the clk and data lanes to get ready during DSI enable. [0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E SoC TRM TRM Link: http://www.ti.com/lit/pdf/spruil1 Fixes: e19233955d9e ("drm/bridge: Add Cadence DSI driver") Cc: stable@vger.kernel.org Tested-by: Dominik Haller Reviewed-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Signed-off-by: Aradhya Bhatia Signed-off-by: Aradhya Bhatia --- drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/d= rm/bridge/cadence/cdns-dsi-core.c index 741d676b8266..93c3d5f1651d 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -776,7 +776,7 @@ static void cdns_dsi_bridge_atomic_enable(struct drm_br= idge *bridge, struct drm_connector *connector; unsigned long tx_byte_period; struct cdns_dsi_cfg dsi_cfg; - u32 tmp, reg_wakeup, div; + u32 tmp, reg_wakeup, div, status; int nlanes; =20 if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0)) @@ -796,6 +796,19 @@ static void cdns_dsi_bridge_atomic_enable(struct drm_b= ridge *bridge, cdns_dsi_hs_init(dsi); cdns_dsi_init_link(dsi); =20 + /* + * Now that the DSI Link and DSI Phy are initialized, + * wait for the CLK and Data Lanes to be ready. + */ + tmp =3D CLK_LANE_RDY; + for (int i =3D 0; i < nlanes; i++) + tmp |=3D DATA_LANE_RDY(i); + + if (readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status, + (tmp =3D=3D (status & tmp)), 100, 500000)) + dev_err(dsi->base.dev, + "Timed Out: DSI-DPhy Clock and Data Lanes not ready.\n"); + writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa), dsi->regs + VID_HSIZE1); writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact), --=20 2.34.1