From nobody Fri Dec 19 18:28:19 2025 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99A8C3597B; Sat, 29 Mar 2025 09:46:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743241613; cv=none; b=mK2HPVbj36VWosFWFeaFb38NGFBLffBWPRdj1pD57oMunkp5APVPTjn15fM/rMeqL+RnPy1Um+Pt/35OqdSifUPuWjYJ+ipHUW85eyzTqfRo13ngrG3FkHZY30rZEyy9X7FhPQSMU0JmTSTpY16UIsW6UQ8fT5MyW25LIoLKJIU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743241613; c=relaxed/simple; bh=fx0U0BsVwzUnXIltjtVO8GJ3KTNVCue7/7UDg0FwFOU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tv/zfH8c+Vekz1ZylphNm4btDbPY36Znkm7E0c1OoJM1/lOk9YD5e+xMdZ3eK7CGPNt71zt3zU1xetpMzz2Y4hM/ZC27Xvs5Og/r45gv06QrIcc/dsC5uwhS3rYadDodZ1BYrPxIDCO16p70PqbVmDdI53L+5hjgEBR1CCXHa8o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hwN3Qs8N; arc=none smtp.client-ip=209.85.216.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hwN3Qs8N" Received: by mail-pj1-f49.google.com with SMTP id 98e67ed59e1d1-30332dfc820so5192941a91.2; Sat, 29 Mar 2025 02:46:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743241611; x=1743846411; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oTiQ/wKhfqa/xxuKIhOYw+HDs40Fp85msPOPKWuOVwM=; b=hwN3Qs8NWSmApUvBmv8a9/MmiPdJy48c34KETSv3AJxadK6qDTHvgfuI/jfG2ZrU6D peVELVkix3Rygi9vYyKnJp/ZdX3p4ehuWm2pnGaKnia8XsK7GDcRMozfUnmIlmIPXfPR 0wNeo7/3nSPcVXJt4/QN0kxcarcweFlHpZ4tiURWicPwJTg7HK8XaOpXvopEPDyIeWZ8 cxAx7+HtLKam3SkMEUzONbde/1/9WABbeXro0XdPMtFTkbqBHXgOBhCngPbS+Haa1ZZY sYiAatjqisQC2B24p5WUb2F88W/H8ztcMnQOtxe8PczK++8wINzrzqiAKrhGAarADirp sNgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743241611; x=1743846411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oTiQ/wKhfqa/xxuKIhOYw+HDs40Fp85msPOPKWuOVwM=; b=c3jBpRGJKPQhwTmc2LeWbWfPfiYFGQyn9ysWzTLVzPXPlpa4Sd9cb77rEU9hxY4SwV BlwhOXXMWWq9r4t1FAcuM/TpIcGmoK0TfSHHxnYPITp6no1lGJb9ZDgNz8vwTVxPQsTU 9h8RV1BS+fjIThXalHTCx+ZIXJVR7t8AUcFfAIvRIQojdpKlq8B2M3qOSF4krGeD9XXw Mu1wgq7XmpAGMZSi5iwXeQUS/EU0GMbpdmmPjUrV6vwJ8RpGr5wRHFiPm4Y2+AYFjnvr +OIOacAdlPm55m/2FHdLVYQfyRCcSXgp582FDf4MrAATrHaWPc0tvaLeJSn2STt/EtQX /XLw== X-Forwarded-Encrypted: i=1; AJvYcCVDf+v9BgVOL3EfVWpqLJYVe9Ew7ltaTtocEn16aCIEO44roCiuZI6faqmHR6fdd60h6+QdV8BU8rwzF10=@vger.kernel.org, AJvYcCWlzvwyvtt3cWxzhLAd51u6sH68mM0aollKultpjUouuCWzZ+3gs6Fq/7k4xAB8H/SXmCLwKQNOrAc/mVxtBlA=@vger.kernel.org X-Gm-Message-State: AOJu0YwfxqhGUv/YMVgJJ/HlHjKWxbCL8eld5ladftgBDHGn0iC2y/hJ ehB3ipYE5YT/YSv9yOXaH2CNDoX8k2ciRTPODxR176yP+gXd/T5vunWWpQ== X-Gm-Gg: ASbGncsfJgxaoB2vQc0qa6MedNS6duMtYsMSg+om/pntC/K6O047u2+ipL2+t9QoGya ebEr4h2pUIC6Shfj1epwKoEq/YKCo07XjMvRwhubg4TYij6RjosYKVwp8Uhg0bLBtzKDxyZswnS YqgnuslozF5IwJdob4z3gEJ0cVC+Dow/ZEgsVrVvVh2g7GI0RrmeXdils+5LANuRkp4V53xQM8Q gUdV1ls0YaMOZg0xRnMymamnJjsk1MsLrTPgP5lqsCr3q6+qXGORjeVLPeoQCzfEI2pMx/1SR6F QcAqgg0lBNXVH+3WOew8fimBfxO7TRmIcYTN X-Google-Smtp-Source: AGHT+IEIEHlYMKuidHwWa1Dt4UO/BKZih2t+w67XaBoqkzGVVw6EpCmXTv3JTT3ij2BczqTlkE15ng== X-Received: by 2002:a17:90b:1d48:b0:2fe:b774:3ec8 with SMTP id 98e67ed59e1d1-305321471fcmr3165962a91.23.1743241610661; Sat, 29 Mar 2025 02:46:50 -0700 (PDT) Received: from valdaarhun.. ([2401:4900:1c44:e4e:6e69:d5cb:5b5a:ea6]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3039f6b31fbsm5680573a91.40.2025.03.29.02.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Mar 2025 02:46:50 -0700 (PDT) From: Sahil Siddiq X-Google-Original-From: Sahil Siddiq To: jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com Cc: sahilcdq@proton.me, linux-openrisc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 1/3] openrisc: Refactor struct cpuinfo_or1k to reduce duplication Date: Sat, 29 Mar 2025 15:16:20 +0530 Message-ID: <20250329094622.94919-2-sahilcdq@proton.me> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250329094622.94919-1-sahilcdq@proton.me> References: <20250329094622.94919-1-sahilcdq@proton.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The "cpuinfo_or1k" structure currently has identical data members for different cache components. Remove these fields out of struct cpuinfo_or1k and into its own struct. This reduces duplication while keeping cpuinfo_or1k extensible so more cache descriptors can be added in the future. Also add a new field "sets" to the new structure. Signed-off-by: Sahil Siddiq --- No change from v3 -> v4/v5. Changes from v1/v2 -> v3: - arch/openrisc/kernel/setup.c: (print_cpuinfo): 1. Cascade changes made to struct cpuinfo_or1k. 2. These lines are ultimately shifted to the new file created in patch #3. (setup_cpuinfo): Likewise. (show_cpuinfo): Likewise. arch/openrisc/include/asm/cpuinfo.h | 16 +++++----- arch/openrisc/kernel/setup.c | 45 ++++++++++++++--------------- 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/as= m/cpuinfo.h index 5e4744153d0e..82f5d4c06314 100644 --- a/arch/openrisc/include/asm/cpuinfo.h +++ b/arch/openrisc/include/asm/cpuinfo.h @@ -15,16 +15,18 @@ #ifndef __ASM_OPENRISC_CPUINFO_H #define __ASM_OPENRISC_CPUINFO_H =20 +struct cache_desc { + u32 size; + u32 sets; + u32 block_size; + u32 ways; +}; + struct cpuinfo_or1k { u32 clock_frequency; =20 - u32 icache_size; - u32 icache_block_size; - u32 icache_ways; - - u32 dcache_size; - u32 dcache_block_size; - u32 dcache_ways; + struct cache_desc icache; + struct cache_desc dcache; =20 u16 coreid; }; diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c index be56eaafc8b9..66207cd7bb9e 100644 --- a/arch/openrisc/kernel/setup.c +++ b/arch/openrisc/kernel/setup.c @@ -115,16 +115,16 @@ static void print_cpuinfo(void) =20 if (upr & SPR_UPR_DCP) printk(KERN_INFO - "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n", - cpuinfo->dcache_size, cpuinfo->dcache_block_size, - cpuinfo->dcache_ways); + "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)= \n", + cpuinfo->dcache.size, cpuinfo->dcache.block_size, + cpuinfo->dcache.sets, cpuinfo->dcache.ways); else printk(KERN_INFO "-- dcache disabled\n"); if (upr & SPR_UPR_ICP) printk(KERN_INFO - "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n", - cpuinfo->icache_size, cpuinfo->icache_block_size, - cpuinfo->icache_ways); + "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)= \n", + cpuinfo->icache.size, cpuinfo->icache.block_size, + cpuinfo->icache.sets, cpuinfo->icache.ways); else printk(KERN_INFO "-- icache disabled\n"); =20 @@ -156,7 +156,6 @@ void __init setup_cpuinfo(void) { struct device_node *cpu; unsigned long iccfgr, dccfgr; - unsigned long cache_set_size; int cpu_id =3D smp_processor_id(); struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[cpu_id]; =20 @@ -165,18 +164,18 @@ void __init setup_cpuinfo(void) panic("Couldn't find CPU%d in device tree...\n", cpu_id); =20 iccfgr =3D mfspr(SPR_ICCFGR); - cpuinfo->icache_ways =3D 1 << (iccfgr & SPR_ICCFGR_NCW); - cache_set_size =3D 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); - cpuinfo->icache_block_size =3D 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); - cpuinfo->icache_size =3D - cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size; + cpuinfo->icache.ways =3D 1 << (iccfgr & SPR_ICCFGR_NCW); + cpuinfo->icache.sets =3D 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); + cpuinfo->icache.block_size =3D 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); + cpuinfo->icache.size =3D + cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_s= ize; =20 dccfgr =3D mfspr(SPR_DCCFGR); - cpuinfo->dcache_ways =3D 1 << (dccfgr & SPR_DCCFGR_NCW); - cache_set_size =3D 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); - cpuinfo->dcache_block_size =3D 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); - cpuinfo->dcache_size =3D - cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size; + cpuinfo->dcache.ways =3D 1 << (dccfgr & SPR_DCCFGR_NCW); + cpuinfo->dcache.sets =3D 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); + cpuinfo->dcache.block_size =3D 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); + cpuinfo->dcache.size =3D + cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_s= ize; =20 if (of_property_read_u32(cpu, "clock-frequency", &cpuinfo->clock_frequency)) { @@ -320,14 +319,14 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV); } seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ); - seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size); + seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size); seq_printf(m, "dcache block size\t: %d bytes\n", - cpuinfo->dcache_block_size); - seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways); - seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size); + cpuinfo->dcache.block_size); + seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways); + seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size); seq_printf(m, "icache block size\t: %d bytes\n", - cpuinfo->icache_block_size); - seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways); + cpuinfo->icache.block_size); + seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways); seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n", 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); --=20 2.48.1 From nobody Fri Dec 19 18:28:19 2025 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88B6D1B6CE5; Sat, 29 Mar 2025 09:46:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743241617; cv=none; b=G60c8wymy515dLyI9N4ZqeMcThkldbMweRiagOeVLS4jCeVWq/7dvxQtz2qIL0Xp4L6UxtBOBklZxvrRVpzcWGYLg2VaZh/Fqdva5N0lLiYH5Ejs81Ln7gk03dQni2djJlqdbHWN9QDDATLHusQ/6+8rtJvZ8zsU7Yh3ne+l9Ao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743241617; c=relaxed/simple; bh=rTVPWsX3Qowb9ZaDN5A7csWAl3V+PvDzkzd33zr1nOw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WztPj4tBjnxXjTEjf8nk+KCkkaiAM/RbSdzFaRKTtonzipV6M1gY+cZsmp5JwsHqX1nqVlaE445YPbEvg3BWyjxMovQ+l4/kD3h2rwfkuZ32FOOh0ucHVgj6hNULKYGXI8Y7vzctRW6vCj2gLq8t1bkiuRNyHtOTirgzF4lV5QM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=F9r8xYdr; arc=none smtp.client-ip=209.85.216.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="F9r8xYdr" Received: by mail-pj1-f50.google.com with SMTP id 98e67ed59e1d1-2ff797f8f1bso4697601a91.3; Sat, 29 Mar 2025 02:46:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743241615; x=1743846415; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HYyBFOZ/eRDHZzTnt9tAVXYoVvRY1rvI0I9fOEyba5I=; b=F9r8xYdrJ3odtvwXI1BMF8qQjsvKeCScNMzLQbwp2XCYyPM7DJsK2SujiL98ZFqwwe XJKXCvJrrIc8M2LmGnZOggYOIecJYHZ84PM/HXaGV6tnkKrERPxB9wcHEqXmU+Hsfa1S QmYTcsAr/D/RPA5vszeVe+9MOGmh6iopGV/cSnYt+QEf5MOB2zunEPGE79f/NWa+GS8x QDU2t9277hvzdk3rNYlBNd/AYLrkS5MsGFeGc46CqXLqGLGyC9zY794DjQHShhO6O+dg KL4F5qwKsg07EhegbiE1eW3VmUR+VIBNBQ8KFPUQSjUUOFXezebHc//Wo9QKJDPO8NB3 vGrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743241615; x=1743846415; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HYyBFOZ/eRDHZzTnt9tAVXYoVvRY1rvI0I9fOEyba5I=; b=kDuS0tClqI95sP9bvhHRZpbhIfCbEH9hRIcFK15z9uHmfpSbAQNfM38HHX4l2or0ia u5uZWmjVu4Ud1/PR17LJzP5Y2aaTpjI9qCcxmsngE+mL2B6xSHuvI8looD1A/onNQ2fE ZYMAhRfjQcgBMEhJ3I2rjFKoxYCa3avLRg82XJaWBpqIQz6tIGZA4M0FutdIDlPfmW7b SxEc/IPOD7ryT3/MH/MlmBzU8sTZoqPE1OfVfydOVHCybU/99Zh8OuP+eWumMQHyZpmv nXNIXiGAq/G5/r4MW6mCygZKjQKEmzJycrzZgZ7vA89IJqajpTZuIwmDT3j3ttBsji3y 9z3A== X-Forwarded-Encrypted: i=1; AJvYcCVsJArA42NrVuxzlSs/lkVFsqTqUv/Y1K+jyjtglk7PdS3rvvT3DNCW6LOe7QlcPpjcy8+8JmkD/oBXgec=@vger.kernel.org, AJvYcCWMayCp7fgrmgDF1FsVopr1BLKAH1V8nmXqN79DPiihz/WOOrErmoHgvKufOWVbxw5rfgYY04NEiw2zqHD1Eos=@vger.kernel.org X-Gm-Message-State: AOJu0Yw0VBFzQ1zwEwvztlmDYb5j25IYiimGxPJi3QDGhRLydsw/8Ztv FS5k5aHk28e4bjoXy+B+0spO73rg4fX5nuaSF7LHBpZSlbrheeDy X-Gm-Gg: ASbGnctqR6D5VCw0ILW6st3nr1arN+yBA5fL8ISxH9DRJyZy/J7+6ZPuVfJ0Xh+0Gtz SrP12M9ADDsKXahtKgRzipZdH++Uz6rA/mJPBwGSfIB8tykWLUbffJrkOVXljtGFk6N05lttcLU qwYcgwP8YKIxMsU1auGNTgRXyWt8Ufo9cP9XVpR7pR9egoBRZTj2DJRqtQFsj0TNWYC/V18BWVt KClJ63rN9YbVpEQDfbLOQBMFSKtDVbfJc1dW7lETPCVasI0DlRkSeuvthiuLMR7XdVDz8WsGkjZ HF/lzoA/u5x6oWiZrawE0DCCSGa6hKPqzalr X-Google-Smtp-Source: AGHT+IFv6jmMUddVsWN6oteEsmJpZ6KB6MAgHWa3Y/TIAGbULB/Q8laKhXlpMhmc43QkY+m+wB8OQg== X-Received: by 2002:a17:90b:1b0f:b0:2ff:5e4e:861 with SMTP id 98e67ed59e1d1-305321653f4mr3395586a91.24.1743241614755; Sat, 29 Mar 2025 02:46:54 -0700 (PDT) Received: from valdaarhun.. ([2401:4900:1c44:e4e:6e69:d5cb:5b5a:ea6]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3039f6b31fbsm5680573a91.40.2025.03.29.02.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Mar 2025 02:46:54 -0700 (PDT) From: Sahil Siddiq X-Google-Original-From: Sahil Siddiq To: jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com Cc: sahilcdq@proton.me, linux-openrisc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/3] openrisc: Introduce new utility functions to flush and invalidate caches Date: Sat, 29 Mar 2025 15:16:21 +0530 Message-ID: <20250329094622.94919-3-sahilcdq@proton.me> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250329094622.94919-1-sahilcdq@proton.me> References: <20250329094622.94919-1-sahilcdq@proton.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the OpenRISC architecture manual, the dcache and icache may not be present. When these caches are present, the invalidate and flush registers may be absent. The current implementation does not perform checks to verify their presence before utilizing cache registers, or invalidating and flushing cache blocks. Introduce new functions to detect the presence of cache components and related special-purpose registers. There are a few places where a range of addresses have to be flushed or invalidated and the implementation is duplicated. Introduce new utility functions and macros that generalize this implementation and reduce duplication. Signed-off-by: Sahil Siddiq --- Changes from v4 -> v5: - arch/openrisc/include/asm/cpuinfo.h: Remove cb_inv_flush_is_implemented. - arch/openrisc/mm/cache.c: (cpu_cache_is_present): Shift definition to the top. (cb_inv_flush_is_implemented): Remove function. - arch/openrisc/mm/cache.c: (cpu_cache_is_present): Fix condition. Changes from v3 -> v4: - arch/openrisc/include/asm/cpuinfo.h: Move new definitions to cache.c. - arch/openrisc/mm/cache.c: (cache_loop): Split function. (cache_loop_page): New function. (cpu_cache_is_present): Move definition here. (cb_inv_flush_is_implemented): Move definition here. Changes from v2 -> v3: - arch/openrisc/include/asm/cacheflush.h: Declare new functions and macros. - arch/openrisc/include/asm/cpuinfo.h: Implement new functions. (cpu_cache_is_present): 1. The implementation of this function was strewn all over the place in the previous versions. 2. Fix condition. The condition in the previous version was incorrect. (cb_inv_flush_is_implemented): New function. - arch/openrisc/kernel/dma.c: Use new functions. - arch/openrisc/mm/cache.c: (cache_loop): Extend function. (local_*_page_*): Use new cache_loop interface. (local_*_range_*): Implement new functions. - arch/openrisc/mm/init.c: Use new functions. arch/openrisc/include/asm/cacheflush.h | 17 ++++++++ arch/openrisc/include/asm/cpuinfo.h | 8 ++++ arch/openrisc/kernel/dma.c | 18 ++------- arch/openrisc/mm/cache.c | 56 +++++++++++++++++++++----- arch/openrisc/mm/init.c | 5 ++- 5 files changed, 79 insertions(+), 25 deletions(-) diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include= /asm/cacheflush.h index 984c331ff5f4..0e60af486ec1 100644 --- a/arch/openrisc/include/asm/cacheflush.h +++ b/arch/openrisc/include/asm/cacheflush.h @@ -23,6 +23,9 @@ */ extern void local_dcache_page_flush(struct page *page); extern void local_icache_page_inv(struct page *page); +extern void local_dcache_range_flush(unsigned long start, unsigned long en= d); +extern void local_dcache_range_inv(unsigned long start, unsigned long end); +extern void local_icache_range_inv(unsigned long start, unsigned long end); =20 /* * Data cache flushing always happen on the local cpu. Instruction cache @@ -38,6 +41,20 @@ extern void local_icache_page_inv(struct page *page); extern void smp_icache_page_inv(struct page *page); #endif /* CONFIG_SMP */ =20 +/* + * Even if the actual block size is larger than L1_CACHE_BYTES, paddr + * can be incremented by L1_CACHE_BYTES. When paddr is written to the + * invalidate register, the entire cache line encompassing this address + * is invalidated. Each subsequent reference to the same cache line will + * not affect the invalidation process. + */ +#define local_dcache_block_flush(addr) \ + local_dcache_range_flush(addr, addr + L1_CACHE_BYTES) +#define local_dcache_block_inv(addr) \ + local_dcache_range_inv(addr, addr + L1_CACHE_BYTES) +#define local_icache_block_inv(addr) \ + local_icache_range_inv(addr, addr + L1_CACHE_BYTES) + /* * Synchronizes caches. Whenever a cpu writes executable code to memory, t= his * should be called to make sure the processor sees the newly written code. diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/as= m/cpuinfo.h index 82f5d4c06314..3cfc4cf0b019 100644 --- a/arch/openrisc/include/asm/cpuinfo.h +++ b/arch/openrisc/include/asm/cpuinfo.h @@ -15,6 +15,9 @@ #ifndef __ASM_OPENRISC_CPUINFO_H #define __ASM_OPENRISC_CPUINFO_H =20 +#include +#include + struct cache_desc { u32 size; u32 sets; @@ -34,4 +37,9 @@ struct cpuinfo_or1k { extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS]; extern void setup_cpuinfo(void); =20 +/* + * Check if the cache component exists. + */ +extern bool cpu_cache_is_present(const unsigned int cache_type); + #endif /* __ASM_OPENRISC_CPUINFO_H */ diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c index b3edbb33b621..3a7b5baaa450 100644 --- a/arch/openrisc/kernel/dma.c +++ b/arch/openrisc/kernel/dma.c @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include =20 @@ -24,9 +25,6 @@ static int page_set_nocache(pte_t *pte, unsigned long addr, unsigned long next, struct mm_walk *walk) { - unsigned long cl; - struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[smp_processor_id()]; - pte_val(*pte) |=3D _PAGE_CI; =20 /* @@ -36,8 +34,7 @@ page_set_nocache(pte_t *pte, unsigned long addr, flush_tlb_kernel_range(addr, addr + PAGE_SIZE); =20 /* Flush page out of dcache */ - for (cl =3D __pa(addr); cl < __pa(next); cl +=3D cpuinfo->dcache_block_si= ze) - mtspr(SPR_DCBFR, cl); + local_dcache_range_flush(__pa(addr), __pa(next)); =20 return 0; } @@ -98,21 +95,14 @@ void arch_dma_clear_uncached(void *cpu_addr, size_t siz= e) void arch_sync_dma_for_device(phys_addr_t addr, size_t size, enum dma_data_direction dir) { - unsigned long cl; - struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[smp_processor_id()]; - switch (dir) { case DMA_TO_DEVICE: /* Flush the dcache for the requested range */ - for (cl =3D addr; cl < addr + size; - cl +=3D cpuinfo->dcache_block_size) - mtspr(SPR_DCBFR, cl); + local_dcache_range_flush(addr, addr + size); break; case DMA_FROM_DEVICE: /* Invalidate the dcache for the requested range */ - for (cl =3D addr; cl < addr + size; - cl +=3D cpuinfo->dcache_block_size) - mtspr(SPR_DCBIR, cl); + local_dcache_range_inv(addr, addr + size); break; default: /* diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c index eb43b73f3855..7bdd07cfca60 100644 --- a/arch/openrisc/mm/cache.c +++ b/arch/openrisc/mm/cache.c @@ -14,31 +14,70 @@ #include #include #include +#include #include =20 -static __always_inline void cache_loop(struct page *page, const unsigned i= nt reg) +/* + * Check if the cache component exists. + */ +bool cpu_cache_is_present(const unsigned int cache_type) { - unsigned long paddr =3D page_to_pfn(page) << PAGE_SHIFT; - unsigned long line =3D paddr & ~(L1_CACHE_BYTES - 1); + unsigned long upr =3D mfspr(SPR_UPR); + unsigned long mask =3D SPR_UPR_UP | cache_type; + + return !((upr & mask) ^ mask); +} + +static __always_inline void cache_loop(unsigned long paddr, unsigned long = end, + const unsigned int reg, const unsigned int cache_type) +{ + if (!cpu_cache_is_present(cache_type)) + return; =20 - while (line < paddr + PAGE_SIZE) { - mtspr(reg, line); - line +=3D L1_CACHE_BYTES; + while (paddr < end) { + mtspr(reg, paddr); + paddr +=3D L1_CACHE_BYTES; } } =20 +static void cache_loop_page(struct page *page, const unsigned int reg, + const unsigned int cache_type) +{ + unsigned long paddr =3D page_to_pfn(page) << PAGE_SHIFT; + unsigned long end =3D paddr + PAGE_SIZE; + + paddr &=3D ~(L1_CACHE_BYTES - 1); + + cache_loop(paddr, end, reg, cache_type); +} + void local_dcache_page_flush(struct page *page) { - cache_loop(page, SPR_DCBFR); + cache_loop_page(page, SPR_DCBFR, SPR_UPR_DCP); } EXPORT_SYMBOL(local_dcache_page_flush); =20 void local_icache_page_inv(struct page *page) { - cache_loop(page, SPR_ICBIR); + cache_loop_page(page, SPR_ICBIR, SPR_UPR_ICP); } EXPORT_SYMBOL(local_icache_page_inv); =20 +void local_dcache_range_flush(unsigned long start, unsigned long end) +{ + cache_loop(start, end, SPR_DCBFR, SPR_UPR_DCP); +} + +void local_dcache_range_inv(unsigned long start, unsigned long end) +{ + cache_loop(start, end, SPR_DCBIR, SPR_UPR_DCP); +} + +void local_icache_range_inv(unsigned long start, unsigned long end) +{ + cache_loop(start, end, SPR_ICBIR, SPR_UPR_ICP); +} + void update_cache(struct vm_area_struct *vma, unsigned long address, pte_t *pte) { @@ -58,4 +97,3 @@ void update_cache(struct vm_area_struct *vma, unsigned lo= ng address, sync_icache_dcache(folio_page(folio, nr)); } } - diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c index d0cb1a0126f9..46b8720db08e 100644 --- a/arch/openrisc/mm/init.c +++ b/arch/openrisc/mm/init.c @@ -35,6 +35,7 @@ #include #include #include +#include =20 int mem_init_done; =20 @@ -176,8 +177,8 @@ void __init paging_init(void) barrier(); =20 /* Invalidate instruction caches after code modification */ - mtspr(SPR_ICBIR, 0x900); - mtspr(SPR_ICBIR, 0xa00); + local_icache_block_inv(0x900); + local_icache_block_inv(0xa00); =20 /* New TLB miss handlers and kernel page tables are in now place. * Make sure that page flags get updated for all pages in TLB by --=20 2.48.1 From nobody Fri Dec 19 18:28:19 2025 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6754F1B2194; Sat, 29 Mar 2025 09:47:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743241622; cv=none; b=o8fiDODghg0ihkAbNpChjluB//ewSBXHhiMYb0+kIQdxYJ0apWhcdG23eLKpRiMg1mPuxr84DY3QU0T8qzlm1C6JztoIteSscV8tFm6iHmnb5fZdp2/iaplQC7kWNTn9ethLs1sptr806CPmhYwhHBNvNnAq+pF4yuR0vhLzCls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743241622; c=relaxed/simple; bh=wQDzDPA+qW+Rg0Qk32WQ6KzPgriI/m9cGtZnihr/STw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NKVcAGYt73lgFn9HcTMjrKoJtJhc5qlwVGiQIQQo9lbydHwleYq6Sy8sbfHUHlFc8/FMRjE209zSaWtPbRRk3XcqSO/z9xcMUts2PSBPDI96u7cgj8WAa9dE36dcpwcTcl0zLZ0E+/bF2yUTfqNuJW2DBJT/uvq/do13pL7gkYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=dflrB+4A; arc=none smtp.client-ip=209.85.216.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="dflrB+4A" Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-3031354f134so3981809a91.3; Sat, 29 Mar 2025 02:47:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1743241619; x=1743846419; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MB//eABbA+sUDJU5vA5poS1PnshzB5aeueAsSvx051c=; b=dflrB+4A/QuFEzE8gRxJAlBHEB0gEi11/RLNttYuzmEP+4sKjPvqw1xixGO3KhyafU oTwkEng/2EWXPZ4k0WDJSWePb2SdnCa8/NrmqJec/tpAoTUyE0lWaEIJoYaNPERMBEGd rH5e7g4df3Go6oiXDqw08LIiFEAIFz/VKLKrzMb+fHNQzqhEr9IdkIf8zw+BqDYAkUsB YEVQ3fczbgUiBXGA2eIJBs3dvf/bfWTOnsKml8kC/S8M7cMRuFj5vXNCqAMD5R9TeXTH VhPNBbpkTz2UFbz0W9q4Tk85YceuuV8KIU/PZX6Vtajl1W5BWpAZFovcLeJT/SrhFHqi cRfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1743241619; x=1743846419; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MB//eABbA+sUDJU5vA5poS1PnshzB5aeueAsSvx051c=; b=aBNBcou/dToo4GNXHcjviNOwPEscH0M+mFDkvqg2nJcLFBpizouW3bAnRgPoUJYw26 25X8X4Bd/l8zzxPGBEwUXebi2xpIce2NJrS9D9IXL5YYW2S3F1xUrtsVlGxeJaNCcafG 1e2zcPWd2Y91Y/pb2ne9StXqxN7TifxSpvoZ1RbXziplsQWUaMeMZO0lX92gr7mupNd3 OMpRP2ClI9FBSIOBcXlSRdp+SkSPFIQyuyAZ/zkIxU7pA5/lHyP3uT4uoKRx47E6OT2B JUZtil9DDGAooIJYnWssDB/GadaadkMLWBzbxVaXScz4PqD1EQMpESccf1o5xm2LXu6y N0Sw== X-Forwarded-Encrypted: i=1; AJvYcCVsVsvGHs76jcRUsBqYovQzvppVPzQAlI3nIwyHlmXbBgdSB7vTBLxJoZ/RqPgB+ZGxQPRhTCxeb/ACfsg5JfI=@vger.kernel.org, AJvYcCXkSbta2EfRipoXh4T6056VN9WL1+IxfvHCi3cYCLCTTI2fK5ANOtj1dXZS51pLm5VP9ycYckf8Eu3YQAE=@vger.kernel.org X-Gm-Message-State: AOJu0YxAI9Rt2W/u1pTozYZT70Ydjj6QZnSyeOsOOVRi5JLh8CFe4118 C7NNhl9Op9Jqvj8Hw+eB7uN0XmreeyTxhMkkILNKgWrye40QQ4B2OW3zzA== X-Gm-Gg: ASbGncu+q4oyIy5KQfMeZolKuWAx9sZrhq2ag9yj8H04fjCkTjlPEuPA9Nu0aCA6qNW rwaRwJfLhMcYlVzfkw7I2y5ubXJqs4bGRpULLjYOjePum/9o/Qs12hs7gND1jLEvUqoSEvuD4kO BVQep+6kp61CoHAVgP/FcXzsqX+53aLVXty+TYJywZApY6Ugj8iaI7kNq1e5urRE8LM2uItIeQ/ Ij2TomKgQP3SsRDsEukieQWAOpoTUh6M8LAvvTRck5C7bn1q1DR5zcD8ZbxWjw9rN8etGcrIgBY uLD9ad2d4va09K00uXRyN0ci4XzT/IyOnDlz X-Google-Smtp-Source: AGHT+IFhiHEbEkkIPQFBMeCUjDSSg1wxyVGwnIeFvk8SxYJ8uNcnFZJ1JuTghes5dGWR+XcTMR+IfQ== X-Received: by 2002:a17:90b:3c4f:b0:2ee:f550:3848 with SMTP id 98e67ed59e1d1-30531f7c573mr3284391a91.5.1743241619525; Sat, 29 Mar 2025 02:46:59 -0700 (PDT) Received: from valdaarhun.. ([2401:4900:1c44:e4e:6e69:d5cb:5b5a:ea6]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3039f6b31fbsm5680573a91.40.2025.03.29.02.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 29 Mar 2025 02:46:59 -0700 (PDT) From: Sahil Siddiq X-Google-Original-From: Sahil Siddiq To: jonas@southpole.se, stefan.kristiansson@saunalahti.fi, shorne@gmail.com Cc: sahilcdq@proton.me, linux-openrisc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/3] openrisc: Add cacheinfo support Date: Sat, 29 Mar 2025 15:16:22 +0530 Message-ID: <20250329094622.94919-4-sahilcdq@proton.me> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250329094622.94919-1-sahilcdq@proton.me> References: <20250329094622.94919-1-sahilcdq@proton.me> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cacheinfo support for OpenRISC. Currently, a few CPU cache attributes pertaining to OpenRISC processors are exposed along with other unrelated CPU attributes in the procfs file system (/proc/cpuinfo). However, a few cache attributes remain unexposed. Provide a mechanism that the generic cacheinfo infrastructure can employ to expose these attributes via the sysfs file system. These attributes can then be exposed in /sys/devices/system/cpu/cpuX/cache/indexN. Move the implementation to pull cache attributes from the processor's registers from arch/openrisc/kernel/setup.c with a few modifications. This implementation is based on similar work done for MIPS and LoongArch. Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1= .4-rev0.pdf Signed-off-by: Sahil Siddiq --- No change from v4 -> v5. Changes from v3 -> v4: - arch/openrisc/kernel/cacheinfo.c: Fix build warning detected by kernel test robot. Changes from v2 -> v3: - arch/openrisc/kernel/cacheinfo.c: 1. Use new functions introduced in patch #2. 2. Address review comments regarding coding style. - arch/openrisc/kernel/setup.c: (print_cpuinfo): Don't remove detection of UPR register. arch/openrisc/kernel/Makefile | 2 +- arch/openrisc/kernel/cacheinfo.c | 104 +++++++++++++++++++++++++++++++ arch/openrisc/kernel/setup.c | 44 +------------ 3 files changed, 108 insertions(+), 42 deletions(-) create mode 100644 arch/openrisc/kernel/cacheinfo.c diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile index 79129161f3e0..e4c7d9bdd598 100644 --- a/arch/openrisc/kernel/Makefile +++ b/arch/openrisc/kernel/Makefile @@ -7,7 +7,7 @@ extra-y :=3D vmlinux.lds =20 obj-y :=3D head.o setup.o or32_ksyms.o process.o dma.o \ traps.o time.o irq.o entry.o ptrace.o signal.o \ - sys_call_table.o unwinder.o + sys_call_table.o unwinder.o cacheinfo.o =20 obj-$(CONFIG_SMP) +=3D smp.o sync-timer.o obj-$(CONFIG_STACKTRACE) +=3D stacktrace.o diff --git a/arch/openrisc/kernel/cacheinfo.c b/arch/openrisc/kernel/cachei= nfo.c new file mode 100644 index 000000000000..61230545e4ff --- /dev/null +++ b/arch/openrisc/kernel/cacheinfo.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * OpenRISC cacheinfo support + * + * Based on work done for MIPS and LoongArch. All original copyrights + * apply as per the original source declaration. + * + * OpenRISC implementation: + * Copyright (C) 2025 Sahil Siddiq + */ + +#include +#include +#include +#include + +static inline void ci_leaf_init(struct cacheinfo *this_leaf, enum cache_ty= pe type, + unsigned int level, struct cache_desc *cache, int cpu) +{ + this_leaf->type =3D type; + this_leaf->level =3D level; + this_leaf->coherency_line_size =3D cache->block_size; + this_leaf->number_of_sets =3D cache->sets; + this_leaf->ways_of_associativity =3D cache->ways; + this_leaf->size =3D cache->size; + cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map); +} + +int init_cache_level(unsigned int cpu) +{ + struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[smp_processor_id()]; + struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + int leaves =3D 0, levels =3D 0; + unsigned long upr =3D mfspr(SPR_UPR); + unsigned long iccfgr, dccfgr; + + if (!(upr & SPR_UPR_UP)) { + printk(KERN_INFO + "-- no UPR register... unable to detect configuration\n"); + return -ENOENT; + } + + if (cpu_cache_is_present(SPR_UPR_DCP)) { + dccfgr =3D mfspr(SPR_DCCFGR); + cpuinfo->dcache.ways =3D 1 << (dccfgr & SPR_DCCFGR_NCW); + cpuinfo->dcache.sets =3D 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); + cpuinfo->dcache.block_size =3D 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); + cpuinfo->dcache.size =3D + cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_= size; + leaves +=3D 1; + printk(KERN_INFO + "-- dcache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n= ", + cpuinfo->dcache.size, cpuinfo->dcache.block_size, + cpuinfo->dcache.sets, cpuinfo->dcache.ways); + } else + printk(KERN_INFO "-- dcache disabled\n"); + + if (cpu_cache_is_present(SPR_UPR_ICP)) { + iccfgr =3D mfspr(SPR_ICCFGR); + cpuinfo->icache.ways =3D 1 << (iccfgr & SPR_ICCFGR_NCW); + cpuinfo->icache.sets =3D 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); + cpuinfo->icache.block_size =3D 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); + cpuinfo->icache.size =3D + cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_= size; + leaves +=3D 1; + printk(KERN_INFO + "-- icache: %d bytes total, %d bytes/line, %d set(s), %d way(s)\n= ", + cpuinfo->icache.size, cpuinfo->icache.block_size, + cpuinfo->icache.sets, cpuinfo->icache.ways); + } else + printk(KERN_INFO "-- icache disabled\n"); + + if (!leaves) + return -ENOENT; + + levels =3D 1; + + this_cpu_ci->num_leaves =3D leaves; + this_cpu_ci->num_levels =3D levels; + + return 0; +} + +int populate_cache_leaves(unsigned int cpu) +{ + struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[smp_processor_id()]; + struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); + struct cacheinfo *this_leaf =3D this_cpu_ci->info_list; + int level =3D 1; + + if (cpu_cache_is_present(SPR_UPR_DCP)) { + ci_leaf_init(this_leaf, CACHE_TYPE_DATA, level, &cpuinfo->dcache, cpu); + this_leaf->attributes =3D ((mfspr(SPR_DCCFGR) & SPR_DCCFGR_CWS) >> 8) ? + CACHE_WRITE_BACK : CACHE_WRITE_THROUGH; + this_leaf++; + } + + if (cpu_cache_is_present(SPR_UPR_ICP)) + ci_leaf_init(this_leaf, CACHE_TYPE_INST, level, &cpuinfo->icache, cpu); + + this_cpu_ci->cpu_map_populated =3D true; + + return 0; +} diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c index 66207cd7bb9e..a9fb9cc6779e 100644 --- a/arch/openrisc/kernel/setup.c +++ b/arch/openrisc/kernel/setup.c @@ -113,21 +113,6 @@ static void print_cpuinfo(void) return; } =20 - if (upr & SPR_UPR_DCP) - printk(KERN_INFO - "-- dcache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)= \n", - cpuinfo->dcache.size, cpuinfo->dcache.block_size, - cpuinfo->dcache.sets, cpuinfo->dcache.ways); - else - printk(KERN_INFO "-- dcache disabled\n"); - if (upr & SPR_UPR_ICP) - printk(KERN_INFO - "-- icache: %4d bytes total, %2d bytes/line, %d set(s), %d way(s)= \n", - cpuinfo->icache.size, cpuinfo->icache.block_size, - cpuinfo->icache.sets, cpuinfo->icache.ways); - else - printk(KERN_INFO "-- icache disabled\n"); - if (upr & SPR_UPR_DMP) printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n", 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), @@ -155,7 +140,6 @@ static void print_cpuinfo(void) void __init setup_cpuinfo(void) { struct device_node *cpu; - unsigned long iccfgr, dccfgr; int cpu_id =3D smp_processor_id(); struct cpuinfo_or1k *cpuinfo =3D &cpuinfo_or1k[cpu_id]; =20 @@ -163,20 +147,6 @@ void __init setup_cpuinfo(void) if (!cpu) panic("Couldn't find CPU%d in device tree...\n", cpu_id); =20 - iccfgr =3D mfspr(SPR_ICCFGR); - cpuinfo->icache.ways =3D 1 << (iccfgr & SPR_ICCFGR_NCW); - cpuinfo->icache.sets =3D 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); - cpuinfo->icache.block_size =3D 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); - cpuinfo->icache.size =3D - cpuinfo->icache.sets * cpuinfo->icache.ways * cpuinfo->icache.block_s= ize; - - dccfgr =3D mfspr(SPR_DCCFGR); - cpuinfo->dcache.ways =3D 1 << (dccfgr & SPR_DCCFGR_NCW); - cpuinfo->dcache.sets =3D 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); - cpuinfo->dcache.block_size =3D 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); - cpuinfo->dcache.size =3D - cpuinfo->dcache.sets * cpuinfo->dcache.ways * cpuinfo->dcache.block_s= ize; - if (of_property_read_u32(cpu, "clock-frequency", &cpuinfo->clock_frequency)) { printk(KERN_WARNING @@ -293,14 +263,14 @@ static int show_cpuinfo(struct seq_file *m, void *v) unsigned int vr, cpucfgr; unsigned int avr; unsigned int version; +#ifdef CONFIG_SMP struct cpuinfo_or1k *cpuinfo =3D v; + seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid); +#endif =20 vr =3D mfspr(SPR_VR); cpucfgr =3D mfspr(SPR_CPUCFGR); =20 -#ifdef CONFIG_SMP - seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid); -#endif if (vr & SPR_VR_UVRP) { vr =3D mfspr(SPR_VR2); version =3D vr & SPR_VR2_VER; @@ -319,14 +289,6 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV); } seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ); - seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache.size); - seq_printf(m, "dcache block size\t: %d bytes\n", - cpuinfo->dcache.block_size); - seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache.ways); - seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache.size); - seq_printf(m, "icache block size\t: %d bytes\n", - cpuinfo->icache.block_size); - seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache.ways); seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n", 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); --=20 2.48.1