From nobody Thu Dec 18 15:07:24 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D50D52135AC for ; Thu, 27 Mar 2025 11:38:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743075514; cv=none; b=eyTe1w3CqKwsaS1BUPNEBQmdQCCRbpF4NEp13e7SWggcozBvrw9VE0euTe8lZixXbScTi5eaEsb8IjGSKq6hH6ThpQ2wWaPunnICbVokAu3KZZv1rCgPojETW+3F27pYERc0bcEwMbWIdjbNOJwanR/Y5cvritLclIsMouxiYvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743075514; c=relaxed/simple; bh=EB/45fOdmv1cUL/uDvO8sqH8HNU4eG/Ssc3IFomyEYc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RaAmeG7QFQfARE9Sndbgd3pbigPKs5IoZQqgk9bausD3efUyfG9JGufIdtGlfEWjor9WHFgzU0KmxmFqd/eyBtbbIkmLib0uzFqG9iK10YaaF+BosJ8Z6nF5X832M4AfDylmzSQY+Io05510ro7OPYOF6rI4Z/WZfbbGGpz7K68= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BC4A71762; Thu, 27 Mar 2025 04:38:37 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A16C83F58B; Thu, 27 Mar 2025 04:38:30 -0700 (PDT) From: Leo Yan To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Cc: Leo Yan Subject: [PATCH v1 5/9] coresight: Avoid enable programming clock duplicately Date: Thu, 27 Mar 2025 11:37:59 +0000 Message-Id: <20250327113803.1452108-6-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250327113803.1452108-1-leo.yan@arm.com> References: <20250327113803.1452108-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The programming clock is enabled by AMBA bus driver before a dynamic probe. As a result, a CoreSight driver may redundantly enable the same clock. To avoid this, add a check for device type and skip enabling the programming clock for AMBA devices. The returned NULL pointer will be tolerated by the drivers. Fixes: 73d779a03a76 ("coresight: etm4x: Change etm4_platform_driver driver = for MMIO devices") Signed-off-by: Leo Yan --- include/linux/coresight.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/include/linux/coresight.h b/include/linux/coresight.h index b888f6ed59b2..26eb4a61b992 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -476,15 +476,18 @@ static inline bool is_coresight_device(void __iomem *= base) * Returns: * * clk - Clock is found and enabled + * NULL - Clock is not needed as it is managed by the AMBA bus driver * ERROR - Clock is found but failed to enable */ static inline struct clk *coresight_get_enable_apb_pclk(struct device *dev) { - struct clk *pclk; + struct clk *pclk =3D NULL; =20 - pclk =3D devm_clk_get_enabled(dev, "apb_pclk"); - if (IS_ERR(pclk)) - pclk =3D devm_clk_get_enabled(dev, "apb"); + if (!dev_is_amba(dev)) { + pclk =3D devm_clk_get_enabled(dev, "apb_pclk"); + if (IS_ERR(pclk)) + pclk =3D devm_clk_get_enabled(dev, "apb"); + } =20 return pclk; } --=20 2.34.1