From nobody Thu Dec 18 15:07:11 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 97C9E213E71 for ; Thu, 27 Mar 2025 11:38:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743075510; cv=none; b=VDjMnxDnRZFeI7bcd/UfsIZmRoYkUDurTmEdSCtEbA4FVQpQiXy5dW3+gX89lHXunCio4GLyn+e94QbpVGv5pJqZdJbhN+pwcqjj93QYp1jy0LKCWsrOWKo3sJjD6pM9U6St08F7nf9W1N8CCF/aCrzS92SeB7NnbQVZcGjwXXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743075510; c=relaxed/simple; bh=EQFGbzvTss9rSDXk9yWFPy0Lcv6WpAgZfqHHJ2amerU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ksl4nIY4X8FUK8Y55WN/caf6xRNDsz/2osPJk9rvcHoAfVluq/cxcsm0fOzj439xgcnpJ/o3Lx9LRZozVgm3WESCJuEUwLEBlQ3Fca8kQ1RKhzorlpyU0RQo30r3Bo4Q9VCysRASfYJb4nry7Yj+EqdPJDMDGCmhULw1VS6j4e0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 764D81762; Thu, 27 Mar 2025 04:38:33 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 551323F58B; Thu, 27 Mar 2025 04:38:26 -0700 (PDT) From: Leo Yan To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Cc: Leo Yan Subject: [PATCH v1 3/9] coresight: etm4x: Support atclk Date: Thu, 27 Mar 2025 11:37:57 +0000 Message-Id: <20250327113803.1452108-4-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250327113803.1452108-1-leo.yan@arm.com> References: <20250327113803.1452108-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The atclk is an optional clock for the CoreSight ETMv4, but the driver misses to initialize it. This change enables atclk in probe of the ETMv4 driver, and dynamically control the clock during suspend and resume. No need to check the driver data and clock pointer in the runtime suspend and resume, so remove checks. And add error handling in the resume function. Add a minor fix to the comment format when adding the atclk field. Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Signed-off-by: Leo Yan Reviewed-by: Anshuman Khandual --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 20 +++++++++++++++---= -- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +++- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index e5972f16abff..537d57006a25 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2149,6 +2149,10 @@ static int etm4_probe(struct device *dev) if (WARN_ON(!drvdata)) return -ENOMEM; =20 + drvdata->atclk =3D devm_clk_get_optional_enabled(dev, "atclk"); + if (IS_ERR(drvdata->atclk)) + return PTR_ERR(drvdata->atclk); + if (pm_save_enable =3D=3D PARAM_PM_SAVE_FIRMWARE) pm_save_enable =3D coresight_loses_context_with_cpu(dev) ? PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; @@ -2397,8 +2401,8 @@ static int etm4_runtime_suspend(struct device *dev) { struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - if (drvdata->pclk && !IS_ERR(drvdata->pclk)) - clk_disable_unprepare(drvdata->pclk); + clk_disable_unprepare(drvdata->atclk); + clk_disable_unprepare(drvdata->pclk); =20 return 0; } @@ -2406,11 +2410,17 @@ static int etm4_runtime_suspend(struct device *dev) static int etm4_runtime_resume(struct device *dev) { struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_prepare_enable(drvdata->pclk); + if (ret) + return ret; =20 - if (drvdata->pclk && !IS_ERR(drvdata->pclk)) - clk_prepare_enable(drvdata->pclk); + ret =3D clk_prepare_enable(drvdata->atclk); + if (ret) + clk_disable_unprepare(drvdata->pclk); =20 - return 0; + return ret; } #endif =20 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index bd7db36ba197..0c21832b5d69 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -919,7 +919,8 @@ struct etmv4_save_state { =20 /** * struct etm4_drvdata - specifics associated to an ETM component - * @pclk APB clock if present, otherwise NULL + * @pclk: APB clock if present, otherwise NULL + * @atclk: Optional clock for the core parts of the ETMv4. * @base: Memory mapped base address for this component. * @csdev: Component vitals needed by the framework. * @spinlock: Only one at a time pls. @@ -987,6 +988,7 @@ struct etmv4_save_state { */ struct etmv4_drvdata { struct clk *pclk; + struct clk *atclk; void __iomem *base; struct coresight_device *csdev; raw_spinlock_t spinlock; --=20 2.34.1