From nobody Thu Dec 18 15:12:23 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DED37213240 for ; Thu, 27 Mar 2025 11:38:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743075506; cv=none; b=QXEQM26OnWR8q7yhJ12YdCNYqxYASa212SDtwE2c8Ze1rVQnnQoPkIneJKJpPKiRMmLp3nbqxeH6xciwNXJBB090fyZHI8OJUB/zJsclOb2hiqT+k89fDjYfP6D9UUT/m4zua/X/SPOWjqlc6p7EyQyw7rSSUn8x7qIDQnTZgzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743075506; c=relaxed/simple; bh=Lnb0/sDrJ29hcJOejrgiGNU7WVuIJF0Yl6IRWI+LbP8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=RaLYaxaZjEGizaAuYnBNReUtM8nojQ+8RPCkslbhDqHiYqOncKHGK20cP3QhfirD0Shqqeelyh2T438mPDxJ9RFbKxViwickApUzqksJN6hBVT3KGcNroY46FCoGVsQEVIKDDVbbgTXbmbrn6mN/TR5xHR5+0GFFYPHPyFIJLjE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 401791762; Thu, 27 Mar 2025 04:38:29 -0700 (PDT) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.1.196.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 094503F58B; Thu, 27 Mar 2025 04:38:21 -0700 (PDT) From: Leo Yan To: Suzuki K Poulose , Mike Leach , James Clark , Anshuman Khandual , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Greg Kroah-Hartman , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Cc: Leo Yan Subject: [PATCH v1 1/9] coresight: tmc: Support atclk Date: Thu, 27 Mar 2025 11:37:55 +0000 Message-Id: <20250327113803.1452108-2-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250327113803.1452108-1-leo.yan@arm.com> References: <20250327113803.1452108-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The atclk is an optional clock for the CoreSight TMC, but the driver misses to initialize it. In most cases, the TMC shares the same atclk with other CoreSight components. Since these components enable the clock before the TMC device is initialized, the TMC continues properly, which is why we don=E2=80=99t observe any lockup issues. This change enables atclk in probe of the TMC driver. Given the clock is optional, it is possible to return NULL if the clock does not exist. IS_ERR() is tolerant for this case. Dynamically disable and enable atclk during suspend and resume. The clock pointers will never be error values if the driver has successfully probed, and the case of a NULL pointer case will be handled by the clock core layer. The driver data is always valid after probe. Therefore, remove the related checks. Also in the resume flow adds error handling. Fixes: bc4bf7fe98da ("coresight-tmc: add CoreSight TMC driver") Signed-off-by: Leo Yan Reviewed-by: Anshuman Khandual --- drivers/hwtracing/coresight/coresight-tmc-core.c | 22 +++++++++++++++++---= -- drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 5978bcda2556..6aad2acd0378 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -789,6 +789,10 @@ static int __tmc_probe(struct device *dev, struct reso= urce *res) struct coresight_desc desc =3D { 0 }; struct coresight_dev_list *dev_list =3D NULL; =20 + drvdata->atclk =3D devm_clk_get_optional_enabled(dev, "atclk"); + if (IS_ERR(drvdata->atclk)) + return PTR_ERR(drvdata->atclk); + ret =3D -ENOMEM; =20 /* Validity for the resource is already checked by the AMBA core */ @@ -1019,18 +1023,26 @@ static int tmc_runtime_suspend(struct device *dev) { struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev); =20 - if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) - clk_disable_unprepare(drvdata->pclk); + clk_disable_unprepare(drvdata->atclk); + clk_disable_unprepare(drvdata->pclk); + return 0; } =20 static int tmc_runtime_resume(struct device *dev) { struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev); + int ret; =20 - if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) - clk_prepare_enable(drvdata->pclk); - return 0; + ret =3D clk_prepare_enable(drvdata->pclk); + if (ret) + return ret; + + ret =3D clk_prepare_enable(drvdata->atclk); + if (ret) + clk_disable_unprepare(drvdata->pclk); + + return ret; } #endif =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 6541a27a018e..cbb4ba439158 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -210,6 +210,7 @@ struct tmc_resrv_buf { =20 /** * struct tmc_drvdata - specifics associated to an TMC component + * @atclk: optional clock for the core parts of the TMC. * @pclk: APB clock if present, otherwise NULL * @base: memory mapped base address for this component. * @csdev: component vitals needed by the framework. @@ -244,6 +245,7 @@ struct tmc_resrv_buf { * Used by ETR/ETF. */ struct tmc_drvdata { + struct clk *atclk; struct clk *pclk; void __iomem *base; struct coresight_device *csdev; --=20 2.34.1