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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-af93ba10da3sm330889a12.66.2025.03.27.13.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Mar 2025 13:55:01 -0700 (PDT) From: Melody Olvera Date: Thu, 27 Mar 2025 13:54:29 -0700 Subject: [PATCH v3 2/4] arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-sm8750_ufs_master-v3-2-bad1f5398d0a@oss.qualcomm.com> References: <20250327-sm8750_ufs_master-v3-0-bad1f5398d0a@oss.qualcomm.com> In-Reply-To: <20250327-sm8750_ufs_master-v3-0-bad1f5398d0a@oss.qualcomm.com> To: Manivannan Sadhasivam , Alim Akhtar , Avri Altman , Bart Van Assche , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Andy Gross , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nitin Rawat , Manish Pandey , Melody Olvera X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743108898; l=3908; i=melody.olvera@oss.qualcomm.com; s=20241204; h=from:subject:message-id; bh=aupm3BTR72idKP6mY4nPP3V9L9gZbHXhnPEYq5h6keA=; b=EHDIVNxlYy8pZLb66Z4nu6jGqkx/4csbTif+5tcuXlCa+7jSoH+A42PI6arb0rdkIc+rN842R FgXxYM8GV9mDM+pb2ejLv2cfcq0mU86K7YUKBVC6GW9LKU4FlEmBq6y X-Developer-Key: i=melody.olvera@oss.qualcomm.com; a=ed25519; pk=1DGLp3zVYsHAWipMaNZZTHR321e8xK52C9vuAoeca5c= X-Authority-Analysis: v=2.4 cv=cs+bk04i c=1 sm=1 tr=0 ts=67e5bb28 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=nvPRnQvScE_Ve3Vg3kMA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: IyF6vt1PnztVwo5NIeldohUrhQKuENor X-Proofpoint-ORIG-GUID: IyF6vt1PnztVwo5NIeldohUrhQKuENor X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-27_04,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 bulkscore=0 mlxlogscore=973 malwarescore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 phishscore=0 suspectscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503270141 From: Nitin Rawat Add UFS host controller and PHY nodes for SM8750 SoC. Co-developed-by: Manish Pandey Signed-off-by: Manish Pandey Signed-off-by: Nitin Rawat Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 103 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 612b99dc3c55495d06b3577531ec6996554bbbb6..ee96a13dc41980da5e9d61cd697= 21b90dbe34936 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -3092,6 +3093,108 @@ gic_its: msi-controller@16040000 { }; }; =20 + ufs_mem_phy: phy@1d80000 { + compatible =3D "qcom,sm8750-qmp-ufs-phy"; + reg =3D <0x0 0x01d80000 0x0 0x2000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsrcc TCSR_UFS_CLKREF_EN>; + + clock-names =3D "ref", + "ref_aux", + "qref"; + + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + + power-domains =3D <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg =3D <0x0 0x01d84000 0x0 0x3000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 =3D <&ufs_opp_table>; + + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "ufs-ddr", + "cpu-ufs"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x60 0>; + dma-coherent; + + lanes-per-direction =3D <2>; + + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + + #reset-cells =3D <1>; + + status =3D "disabled"; + + ufs_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz =3D /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + }; + apps_rsc: rsc@16500000 { compatible =3D "qcom,rpmh-rsc"; reg =3D <0x0 0x16500000 0x0 0x10000>, --=20 2.48.1