From nobody Wed Dec 17 08:54:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70774190692; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; cv=none; b=GR9dyjFpB5Bs+t4ZMbeqrYA2jLb4SDjfsK1wYCAm3osnASQK5KUzfQi/Gb5JpImUTTLgHF0h9V9seugdcNilJf3g/6wbj/1qfE4BYsXaDl1/N/ytAXUunSHN+TGnNPcpsTHQiiU4KxjfE4peq/Te/RLVW4FixgVArkQU7951EKg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; c=relaxed/simple; bh=xj1/d4nkyU14Uz0z2ygXiCJS8S9VEH7Pg1iUVkAGGlY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rgyCMEm6KDIsM1P++VqtG/rmcxqiLjYIblHzWlItTGddbdIZVBVOgQmQp0Ch5qK1e8LoECErbY7IsD3ijRGDPcKgJxehO1f2ThAHH9uGBmaEPk99scwyKwSdHlY6i3koqH/XoUNlS5xzQkwPxcKFO8vcy6ZR8t9B9K3+kJrqq0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KWCIJNeR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KWCIJNeR" Received: by smtp.kernel.org (Postfix) with ESMTPS id F383AC4CEE8; Thu, 27 Mar 2025 15:52:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743090759; bh=xj1/d4nkyU14Uz0z2ygXiCJS8S9VEH7Pg1iUVkAGGlY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=KWCIJNeR6lDuePraK3O1cPSaZLP7G7Knsk7m4Ltov64ZE/K/A5MY0Cvhyx1sLKTTW HDufXnKWVsJcp9/4A67eSlf0kOy2BAwLU7Exa+7qDANTxZ1ajjEkZdZHPD+8AuoYG1 EwPHlFXw+iCriiuwsUirwiQe7VICG8jZG/AmBNfBs7A+vavftTon5z80o7+lBb6LbN QnNNHG6mLPnV8jyBg6+5dY6Av4nbw3vXmiuDjEP5BbyOLGMyKymIsn1Ii2Z5vIq9/t C99tPZWjH+cnkvx/0G7EmIQPjmtZn61ApFQukGpqSOK6KhBCNzgwE9BNRJSH5U0BQF 0S9/gZs+Rv9QQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCEE8C36010; Thu, 27 Mar 2025 15:52:38 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 27 Mar 2025 16:52:36 +0100 Subject: [PATCH v3 1/8] dt-bindings: arm: fsl: Add GOcontroll Moduline Display Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-1-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=1206; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=7LK5io9tXyJrf5fT7pNPykcX/YAUSsMUIEqjia8Pbmw=; b=Ci9zEyHGluWtFXDpsIS5IxH7Uq6QR2lofbpjZgcJjYhQfKRKhDKVnPBOMXIS0Y82m2RTYDjOl a0oz/fkDTq6AhV5Ddbc2sBre0Do9g/0XdYegz2yqWBIqwmlZIa7JnGt X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Document the compatible strings for the Moduline Display controller. Acked-by: Rob Herring (Arm) Signed-off-by: Maud Spierings --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 1b90870958a22e49355dd1f932bf3d84cd864b5f..ecde2123ea0fae38ef233929c7a= d343812851a58 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1095,6 +1095,7 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board + - gocontroll,moduline-display # GOcontroll Moduline Display = controller - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without fr= ontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control = without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control w= ith 7=E2=80=9D panel --=20 2.49.0 From nobody Wed Dec 17 08:54:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 707BE19B3EE; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; cv=none; b=ek7b1NxRQAVZSJxpQKoc1+5p1uEk1f1QPf5VCE1xGvgfCb0Gcs2qqjpfNk4uopTs1qSHTO5o80fM6GynfP8pNvaUvWu4vFKsT+A/gFyHr+94rw/8Gj1cc7pkQeOlLmCtp19O21IwGY+hXra0+QWhJ5nJXXelN/QB3iH5LlnYiR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; c=relaxed/simple; bh=PzRZADRzEuijueVkCqt3ZlpSUYrgKBPKl6nIf/RYyME=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Oa0mHrZxh9MmGji8OJL7TJdWQUGpTjx5mWA6aNO/pt0IS/GMubi6uZUFT+AvNCzv0QZVcHbrhc0fNOTUzEmxkuvc7U1oozSgW2fI8dPPxgys5exVW1Y7LnLmce5uGjqVd5zGXNywDCliLGDgv2GdDsfcM9A7MEbzbyPL2CAkWrQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bzXYDf5W; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bzXYDf5W" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0E59CC4CEE5; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743090759; bh=PzRZADRzEuijueVkCqt3ZlpSUYrgKBPKl6nIf/RYyME=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bzXYDf5W0vuDYoXNM2nDvVThJh2vj/61892S+bDRQc1Ck0FJGXiBZgpAyQxm1M23e kcwT5DU1LOnkRe2f94HmvzXHL9w3sREdMu9H6aZKTrUYYdkdBtrTaM3hUBDdFu6mkS 7+TU/EkanYnBQtLX4p/NSpvfF/xmH/x33xkXbU/6pfAnncOp5wXvJlhQxMXloyMddp MyxF+PTLjZoUH/ynYWehpIB/zFoB6QFzjfV8f8k8ihBIk7zQx/bRaBsNwWQCqoD6Pp UZrZxce2HD0WB8gFtYdsj4k/KEyvpkzE1eBjtRi9zE3iD8VZPfmMe+qqtol46nEyvo FtkRdOqp6sBMw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3EDAC36013; Thu, 27 Mar 2025 15:52:38 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 27 Mar 2025 16:52:37 +0100 Subject: [PATCH v3 2/8] arm64: dts: imx8mp: Add pinctrl config definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-2-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=1855; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=z8kax1Z8Rt5R5zrqgQhjYmqWGcylyxJuzA+qptS0r3Y=; b=MFpf0P1ysKsaRzFGmcUSr1ybUT56O1owbtlTS0l5JTJH+iNElla6j8L0WeAbV3oNF5nlGGkbz 3GQKUKXpLwDByV4VwrV/LUIIoj4a2wAbtYmHSvNKftHKcM/Yo+yx3FY X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Currently to configure each IOMUXC_SW_PAD_CTL_PAD the raw value of this register is written in the dts, these values are not obvious. Add defines which describe the fields of this register which can be or-ed together to produce readable settings. Acked-by: Rob Herring (Arm) Signed-off-by: Maud Spierings Reviewed-by: Frank Li --- This patch has already been sent in a different group of patches: [1] It was requested there to submit it along with a user, this series also includes some users for it. [1]: https://lore.kernel.org/all/20250218-pinctrl_defines-v2-2-c554cad0e1d2= @gocontroll.com/ --- arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 27 ++++++++++++++++++++++= ++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h b/arch/arm64/bo= ot/dts/freescale/imx8mp-pinfunc.h index 0fef066471ba607be02d0ab15da5a048a8a213a7..34a6d3090926b8d9d7c96d1b0b0= 1be0ed05cbd27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h @@ -6,6 +6,33 @@ #ifndef __DTS_IMX8MP_PINFUNC_H #define __DTS_IMX8MP_PINFUNC_H =20 +/* Drive Strength */ +#define MX8MP_DSE_X1 0x0 +#define MX8MP_DSE_X2 0x4 +#define MX8MP_DSE_X4 0x2 +#define MX8MP_DSE_X6 0x6 + +/* Slew Rate */ +#define MX8MP_FSEL_FAST 0x10 +#define MX8MP_FSEL_SLOW 0x0 + +/* Open Drain */ +#define MX8MP_ODE_ENABLE 0x20 +#define MX8MP_ODE_DISABLE 0x0 + +#define MX8MP_PULL_DOWN 0x0 +#define MX8MP_PULL_UP 0x40 + +/* Hysteresis */ +#define MX8MP_HYS_CMOS 0x0 +#define MX8MP_HYS_SCHMITT 0x80 + +#define MX8MP_PULL_ENABLE 0x100 +#define MX8MP_PULL_DISABLE 0x0 + +/* SION force input mode */ +#define MX8MP_SION 0x40000000 + /* * The pin function ID is a tuple of * --=20 2.49.0 From nobody Wed Dec 17 08:54:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 998F719C56C; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-3-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=938; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=KWBmWJYZAEU0seHj0jSXyh4vIhNFeNg5DppjC874JB8=; b=q/UBBL+LYJA5pcGDSuTQs40AloieOXHbAumcVf25yCzVjg/H2s2t+1xoMynKT5f2gRuEDJ5Xy n1+YUlByj8yCbS1MwzsKrs77zpdgVDBOHmJgkbaqCwiUoY7+lAGBD7+ X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add GOcontroll as unofficial maintainers of the Ka-Ro tx8p-ml81 COM module bindings. This support is not officially done by Ka-Ro electronics, if they at some point will supporting mainline, this should be changed to them. Signed-off-by: Maud Spierings --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 322ee00547f6e494a96d2495092f72148da22bd0..f8ad2c1023016d7f72cccff880e= 3753d71d635b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12752,6 +12752,12 @@ S: Maintained F: Documentation/hwmon/k8temp.rst F: drivers/hwmon/k8temp.c =20 +KA-RO TX8P COM MODULE +M: Maud Spierings +L: devicetree@vger.kernel.org +S: Maintained +F: arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi + KASAN M: Andrey Ryabinin R: Alexander Potapenko --=20 2.49.0 From nobody Wed Dec 17 08:54:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD9DC19DF7D; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; cv=none; b=YcMYsFEokgfj5TEN3cVg461YuEA7bfvqqRE9CZvFRve00sDNKDszwhw+sC/jYSGedi9V3kUYoMj/5zcgOhkQ+UZqPyW1iwlh/iahOiTF+h3QQFuTH4wlPfg+y11muzyP3Qt0DxLXOHRlm1I3wY3WDRWl3UEkAljKYNK5WBYfdA8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; c=relaxed/simple; bh=fruR+HANJtaCS7pv0tIznmn63cohTn5pkBrHDkeQ/js=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sy6mZ0grWyvvQt9ZkzaeIUH0qWIjZAJPaKkOsHGNy6NaUaVL5svnD7OMi370ukugZI/FzFlvcDKV/cuAHwKSwhiv9LZiZYsZuQx0RM5VFztIjwlEpyLUYR4stnNfSGfb9fYX+QHgrbd67vHW/2BiHWT81nD4tWcV6hsTl9Ej8Jw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h7hsl0AM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h7hsl0AM" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3DD63C4CEF2; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743090759; bh=fruR+HANJtaCS7pv0tIznmn63cohTn5pkBrHDkeQ/js=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=h7hsl0AM/22e/bEG6vm7tKzL9hKw5Ffc0SDldeO0CoRADC3nDBKm/BL01FZyWh8+2 YFtV/b5X8OGQuA8Dnx5848jxlcYndwHK6kWDY2i/MUW923jbp86pQe8/nZprdcgpbD fHwwOIg31/FS+S+xwTaRrcNQd4Nw2wWFJjuobtkDK+sd8/H8xsF2VeAirZGf3W+pKH 58M8jQ+WJ3cBzLyhrmUU0tLwem//5qThOUfqjHMhBY+K8a2C5ptcphHiSwI3Ev4Spj xO2JeITNEal+ZdtpA6c/qc8ig1ov5npo0CBjSgGPXQzckUaXHHYIeyZp2kE5lNZi3D NOQVKAz5b9/Aw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33E42C3600B; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 27 Mar 2025 16:52:39 +0100 Subject: [PATCH v3 4/8] MAINTAINERS: add maintainer for the GOcontroll Moduline controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-4-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=784; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=FLQCcTWqYBxzwTgGEyJvwN7uBqYk4J8ig3eGwMbzAQE=; b=wSQBKxI5wiMevTMoYJpi50Xz/fTuH2kMgJsTc630dXJtxeXk41frv+lEF4Skf497B5qsr9dNk Tz0JbNBB6KfBd8mK5U9i3xQfHobGNDwXJ7YW86eWDeeZ93MWRrgQ3sc X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add a maintainer for the GOcontroll Moduline series of controllers. Signed-off-by: Maud Spierings --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f8ad2c1023016d7f72cccff880e3753d71d635b2..123f03d8f8bdeec6bc947044a0c= 46b84764863ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10043,6 +10043,12 @@ L: linux-media@vger.kernel.org S: Maintained F: drivers/media/usb/go7007/ =20 +GOCONTROLL MODULINE CONTROLLERS +M: Maud Spierings +L: devicetree@vger.kernel.org +S: Maintained +F: arch/arm64/boot/dts/freescale/*moduline*.dts* + GOCONTROLL MODULINE MODULE SLOT M: Maud Spierings S: Maintained --=20 2.49.0 From nobody Wed Dec 17 08:54:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFAA019DFA7; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; cv=none; b=SXl62kDINUPJ5SsmNwH9IKK6QRDNpyyaWyiIhwQRLShzpDquTZB4PAWErtzLq86CJ63HNUxzSS//tEI4AHJx7jzqumhRq/2meiNbO4n6UBGwoawUmEIXGqqukj4TNSlCZX/Pz7qJryOiu6qi/uwFBfhFOAQRpOYvaFDjjt699aU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090759; c=relaxed/simple; bh=hf+LTa4cPiIkXOE147WcGauPs8mw816HOZ12faXpxgg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uUCR0FQcp7/WMOwLDFkLULjBWbYnnEyUtWBUGwmFuKAF92woVg5u1AeKzjhSKPRDuLP8WNlkqc2sI6BF2y/M/++lqC49cphsiYrIPV2bSsZ0JomLBF5JNiejRq9ksKGqIDNcYxTYxp3ndQDVvvEZC07Esw5Rrw3gAYABpbw5R20= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hAU+Mp8V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hAU+Mp8V" Received: by smtp.kernel.org (Postfix) with ESMTPS id 52DCCC4CEF4; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743090759; bh=hf+LTa4cPiIkXOE147WcGauPs8mw816HOZ12faXpxgg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hAU+Mp8VKIBN0874ZbvhLVC5T2gWVHkL3xHdgllAN9DL+WGdQln2ysQmgkOnEY6D9 DPKI0b2ypSuuD1H8vkuGT0juxJyoPsh92Am2yvKPI9w0oDDz8Z99keX4LoJ8lXCCKx nXbfY9e2unR0gm6kfA16veMfaacwY7TQQZd0gEKXHSyAH6AScjLl+ET8LJwBI9bwtq ZTh04eCcf5BfqcW3BAsGUxsqEP7YaAnCn9Sj9BC735jeM9twZDFKMnxME6sUcVFMBC DxKCFGnIuAX66PtMSz08tDWX2IBnAxzo1m62+VyjC3gpqM/K/vgZj8AJpq5d8VAkt6 WbPz2sU2lqFKw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49046C36011; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 27 Mar 2025 16:52:40 +0100 Subject: [PATCH v3 5/8] arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-5-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=16023; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=6/4MC2HlxHuUt7vXFjtv43gHyOLPAnTiEY+dSNJgTjU=; b=TM0/4gX5j5+xIbs/GGAwscB3X9+N6baA5aw1C63UOWf4IeY9ehtOyss/VSplu4BxqjkQxYHiO lb8pTHd79+UATNN8JvgYIWcmEtr0XMsBmr9rBBkXkd/Th2qkmmXweIR X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings The Ka-Ro Electronics tx8p-ml81 is a COM based on the imx8mp SOC. It has 2 GB or ram and 8 GB of eMMC storage on board. Add it to enable boards based on this Module Signed-off-by: Maud Spierings --- .../arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi | 549 +++++++++++++++++= ++++ 1 file changed, 549 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi b/arch/arm= 64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..9c4304e909b96afeb62962198da= 377319eda8506 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2020 Lothar Wa=C3=9Fmann + * 2025 Maud Spierings + */ + +#include "imx8mp.dtsi" + +/ { + /* PHY regulator */ + regulator-3v3-etn { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_3v3_etn>; + regulator-name =3D "3v3-etn"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vdd_3v3>; + gpios =3D <&gpio1 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&A53_0 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply =3D <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply =3D <®_vdd_arm>; +}; + + +&eqos { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_eqos>; + pinctrl-1 =3D <&pinctrl_eqos_sleep>; + assigned-clocks =3D <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents =3D <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates =3D <0>, <100000000>, <50000000>; + phy-mode =3D "rmii"; + phy-handle =3D <ðphy0>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ethphy_rst_b>; + reset-gpios =3D <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us =3D <25000>; + + ethphy0: ethernet-phy@0 { + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ethphy_int_b>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <21 IRQ_TYPE_EDGE_FALLING>; + clocks =3D <&clk IMX8MP_CLK_ENET_QOS>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names =3D "SODIMM_152", + "SODIMM_42", + "PMIC_WDOG_B SODIMM_153", + "PMIC_IRQ_B", + "SODIMM_154", + "SODIMM_155", + "SODIMM_156", + "SODIMM_157", + "SODIMM_158", + "SODIMM_159", + "SODIMM_161", + "SODIMM_162", + "SODIMM_34", + "SODIMM_36", + "SODIMM_27", + "SODIMM_28", + "ENET_MDC", + "ENET_MDIO", + "", + "ENET_XTAL1/CLKIN", + "ENET_TXD1", + "ENET_TXD0", + "ENET_TXEN", + "ENET_POWER", + "ENET_COL/CRS_DV", + "ENET_RXER", + "ENET_RXD0", + "ENET_RXD1", + "", + "", + "", + ""; +}; + +&gpio2 { + gpio-line-names =3D "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_51", + "SODIMM_57", + "SODIMM_56", + "SODIMM_52", + "SODIMM_53", + "SODIMM_54", + "SODIMM_55", + "SODIMM_15", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +&gpio3 { + gpio-line-names =3D "", + "", + "EMMC_DS", + "EMMC_DAT5", + "EMMC_DAT6", + "EMMC_DAT7", + "", + "", + "", + "", + "EMMC_DAT0", + "EMMC_DAT1", + "EMMC_DAT2", + "EMMC_DAT3", + "", + "EMMC_DAT4", + "", + "EMMC_CLK", + "EMMC_CMD", + "SODIMM_75", + "SODIMM_145", + "SODIMM_163", + "SODIMM_164", + "SODIMM_165", + "SODIMM_143", + "SODIMM_144", + "SODIMM_72", + "SODIMM_73", + "SODIMM_74", + "SODIMM_93", + "", + ""; +}; + +&gpio4 { + gpio-line-names =3D "SODIMM_98", + "SODIMM_99", + "SODIMM_100", + "SODIMM_101", + "SODIMM_45", + "SODIMM_43", + "SODIMM_105", + "SODIMM_106", + "SODIMM_107", + "SODIMM_108", + "SODIMM_104", + "SODIMM_103", + "SODIMM_115", + "SODIMM_114", + "SODIMM_113", + "SODIMM_112", + "SODIMM_109", + "SODIMM_110", + "SODIMM_95", + "SODIMM_96", + "SODIMM_97", + "ENET_nINT", + "ENET_nRST", + "SODIMM_84", + "SODIMM_87", + "SODIMM_86", + "SODIMM_85", + "SODIMM_83", + "", + "SODIMM_66", + "SODIMM_65", + ""; +}; + +&gpio5 { + gpio-line-names =3D "", + "", + "", + "SODIMM_76", + "SODIMM_81", + "SODIMM_146", + "SODIMM_48", + "SODIMM_46", + "SODIMM_47", + "SODIMM_44", + "SODIMM_49", + "", + "SODIMM_70", + "SODIMM_69", + "PMIC_SCL", + "PMIC_SDA", + "SODIMM_41", + "SODIMM_40", + "SODIMM_148", + "SODIMM_149", + "SODIMM_150", + "SODIMM_151", + "SODIMM_60", + "SODIMM_59", + "SODIMM_64", + "SODIMM_63", + "SODIMM_62", + "SODIMM_61", + "SODIMM_68", + "SODIMM_67", + "", + ""; +}; + +&i2c1 { + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c1>; + pinctrl-1 =3D <&pinctrl_i2c1_gpio>; + clock-frequency =3D <400000>; + scl-gpios =3D <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + pmic@25 { + reg =3D <0x25>; + compatible =3D "nxp,pca9450c"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pmic>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <3 IRQ_TYPE_EDGE_FALLING>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name =3D "vdd-soc"; + regulator-min-microvolt =3D <805000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name =3D "vdd-core"; + regulator-min-microvolt =3D <805000>; + regulator-max-microvolt =3D <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + nxp,dvs-run-voltage =3D <950000>; + nxp,dvs-standby-voltage =3D <850000>; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_nand: BUCK5 { + regulator-name =3D "nvcc-nand"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name =3D "nvcc-dram"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_snvs_1v8: LDO1 { + regulator-name =3D "snvs-1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name =3D "LDO2"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <1150000>; + regulator-always-on; + }; + + reg_vdda_1v8: LDO3 { + regulator-name =3D "vdda-1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + }; + + ldo5_reg: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&usdhc3 { /* eMMC */ + max-frequency =3D <200000000>; + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates =3D <200000000>; + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + bus-width =3D <8>; + vmmc-supply =3D <®_vdd_3v3>; + vqmmc-supply =3D <®_nvcc_nand>; + voltage-ranges =3D <3300 3300>; + non-removable; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_SION) + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER + (MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST) + >; + }; + + pinctrl_eqos_sleep: eqos-sleep-grp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 + (MX8MP_ODE_ENABLE | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_ethphy_int_b: ethphy-int-bgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT) + >; + }; + + pinctrl_ethphy_rst_b: ethphy-rst-bgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 + (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_reg_3v3_etn: reg-3v3-etngrp { + fsl,pins =3D < + MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABL= E) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; 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Thu, 27 Mar 2025 15:52:39 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 27 Mar 2025 16:52:41 +0100 Subject: [PATCH v3 6/8] arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-6-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=16634; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=sGxXlPEp0IYObrLt0XyIE0e57nwcYtizz9HWa0Ky/lg=; b=Mi/La9KCUCOJv/acZyiAR8vghQJglF/NK8FZ78O5UFNWcXqFZ2kuq9kpbLWJxVAbbjSsFzxzR ZkYNOfWfSasD2sH1PI17FzNc6jGj0jSVGr1sBIdZQ+TwUK06OUVmWtV X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings The Moduline Display platform is a part of the wider GOcontroll Moduline ecosystem. These are embedded controllers that focus on modularity with their swappable IO modules. The base Moduline Display board includes a board-to-board connector with various busses to enable adding new display types required by the application. It includes 2 Moduline IO module slots, a simple mono codec/amplifier, a four channel adc, 2 CAN busses, an RTC and optional wifi/bluetooth. busses to the display adapter include: - 4 lane LVDS - 4 lane MIPI-DSI - 4 lane MIPI-CSI - HDMI 2.0a - USB 2.0 - I2S - I2C - SPI Also a couple of GPIO and PWM pins for controlling various ICs on the display adapter board. Signed-off-by: Maud Spierings --- .../imx8mp-tx8p-ml81-moduline-display-106.dtsi | 535 +++++++++++++++++= ++++ 1 file changed, 535 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-displa= y-106.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-displa= y-106.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..a3ab389c9744f5189d5a8a802aa= 4c4ebb9f7b12b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.d= tsi @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2025 GOcontroll B.V. + * Author: Maud Spierings + */ + +#include "imx8mp-tx8p-ml81.dtsi" + +/ { + chassis-type =3D "embedded"; + compatible =3D "gocontroll,moduline-display", "fsl,imx8mp"; + hardware =3D "Moduline Display V1.06"; + + aliases { + ethernet0 =3D &eqos; + mmc0 =3D &usdhc3; + mmc1 =3D &usdhc2; + spi0 =3D &ecspi2; /* spidev number compatibility */ + spi1 =3D &ecspi1; /* spidev number compatibility */ + can0 =3D &flexcan1; + can1 =3D &flexcan2; + rtc0 =3D &rtc_pcf; /* i2c rtc is the main rtc */ + rtc1 =3D &snvs_rtc; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + external-sensor-supply { + compatible =3D "regulator-output"; + vout-supply =3D <®_5v0_sensor>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible =3D "regulator-fixed"; + regulator-name =3D "can1-stby"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1_reg>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio4 3 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible =3D "regulator-fixed"; + regulator-name =3D "can2-stby"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2_reg>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + + reg_1v8_per: regulator-1v8-per { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8-per"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_1v8>; + gpio =3D <&gpio3 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + power-supply =3D <®_3v3_per>; + }; + + reg_3v3_per: regulator-3v3-per { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3-per"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + power-supply =3D <®_6v4>; + }; + + reg_5v0_sensor: regulator-5v0-sensor { + compatible =3D "regulator-fixed"; + regulator-name =3D "5v0-supply-external-sensor"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_5v0_sensor>; + gpio =3D <&gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_5v0: regulator-5v0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + power-supply =3D <®_6v4>; + }; + + reg_6v4: regulator-6v4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "6v4"; + regulator-min-microvolt =3D <6400000>; + regulator-max-microvolt =3D <6400000>; + regulator-always-on; + }; + + sound { + compatible =3D "simple-audio-card"; + simple-audio-card,name =3D "tas2505-audio"; + simple-audio-card,format =3D "i2s"; + simple-audio-card,frame-master =3D <&cpudai>; + simple-audio-card,bitclock-master =3D <&cpudai>; + simple-audio-card,widgets =3D + "Speaker", "Speaker External"; + simple-audio-card,routing =3D + "Speaker", "DAC"; + + cpudai: simple-audio-card,cpu { + sound-dai =3D <&sai6>; + }; + + simple-audio-card,codec { + sound-dai =3D <&tas2505>; + }; + }; + + wifi_powerseq: wifi-powerseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wl_reg>; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <500000>; + reset-gpios =3D <&gpio2 19 GPIO_ACTIVE_LOW>; + }; +}; + +&ecspi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi1>; + cs-gpios =3D < + &gpio2 12 GPIO_ACTIVE_LOW + &gpio1 11 GPIO_ACTIVE_LOW + &gpio1 10 GPIO_ACTIVE_LOW + >; + status =3D "okay"; + + connector@0 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <0>; + reset-gpios =3D <&gpio5 10 GPIO_ACTIVE_LOW>; + sync-gpios =3D <&gpio4 16 GPIO_ACTIVE_HIGH>; + interrupt-parent =3D <&gpio4>; + interrupts =3D <5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply =3D <®_3v3_per>; + vddp-supply =3D <®_5v0>; + vddhpp-supply =3D <®_6v4>; + i2c-bus =3D <&i2c2>; + slot-number =3D <1>; + spi-max-frequency =3D <54000000>; + + }; + + connector@1 { + compatible =3D "gocontroll,moduline-module-slot"; + reg =3D <1>; + reset-gpios =3D <&gpio1 8 GPIO_ACTIVE_LOW>; + sync-gpios =3D <&gpio4 16 GPIO_ACTIVE_HIGH>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + vdd-supply =3D <®_3v3_per>; + vddp-supply =3D <®_5v0>; + vddhpp-supply =3D <®_6v4>; + i2c-bus =3D <&i2c2>; + slot-number =3D <2>; + spi-max-frequency =3D <54000000>; + }; + + adc@2 { + compatible =3D "microchip,mcp3004"; + reg =3D <2>; + spi-max-frequency =3D <2300000>; + vref-supply =3D <®_vdd_3v3>; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + xceiver-supply =3D <®_can1_stby>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + xceiver-supply =3D <®_can2_stby>; + status =3D "okay"; +}; + +/* I2C2 bus to modules */ +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c2>; + pinctrl-1 =3D <&pinctrl_i2c2_gpio>; + sda-gpios =3D <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; +}; + +&i2c4 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&pinctrl_i2c4>; + pinctrl-1 =3D <&pinctrl_i2c4_gpio>; + sda-gpios =3D <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios =3D <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + tas2505: tas2505@18 { + compatible =3D "ti,tas2505"; + reg =3D <0x18>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tas_reset>; + reset-gpios =3D <&gpio3 24 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + + dv-supply =3D <®_1v8_per>; + iov-supply =3D <®_vdd_3v3>; + av-supply =3D <®_1v8_per>; + + clocks =3D <&clk IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>; + clock-names =3D "mclk"; + aic32x4-gpio-func=3D < + 0xff + 0xff + 0xff + 0xff + 0xff + >; + }; + + rtc_pcf: rtc@51 { + compatible =3D "nxp,pcf85063a"; + reg =3D <0x51>; + quartz-load-femtofarads =3D <7000>; + + clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + }; + }; +}; + +/* tas2505 */ +&sai6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sai6>; + status =3D "okay"; + assigned-clocks =3D <&clk IMX8MP_CLK_SAI6>; + assigned-clock-parents =3D <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates =3D <12288000>; + fsl,sai-mclk-direction-output; +}; + +/* debug/external */ +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + uart-has-rtscts; + status =3D "okay"; + + /* muRata 1YN/1DX */ + bluetooth { + compatible =3D "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed =3D <921600>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_bt>; + device-wakeup-gpios =3D <&gpio1 15 GPIO_ACTIVE_HIGH>; + shutdown-gpios =3D <&gpio1 14 GPIO_ACTIVE_HIGH>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <12 IRQ_TYPE_EDGE_FALLING>; + interrupt-names =3D "host-wakeup"; + vddio-supply =3D <®_3v3_per>; + vbat-supply =3D <®_3v3_per>; + }; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb3_phy0 { + status =3D "okay"; +}; + +&usb_dwc3_0 { + dr_mode =3D "peripheral"; +}; + +&usdhc2 { + max-frequency =3D <50000000>; + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates =3D <50000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usdhc2>; + mmc-pwrseq =3D <&wifi_powerseq>; + vmmc-supply =3D <®_3v3_per>; + + cap-power-off-card; + keep-power-in-suspend; + non-removable; + sd-uhs-sdr25; + + status =3D "okay"; + + /* muRata 1YN/1DX */ + wifi@1 { + compatible =3D "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + reg =3D <1>; + brcm,board-type =3D "GOcontroll,moduline"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wl_int>; + interrupt-parent =3D <&gpio1>; + interrupts =3D <13 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "host-wake"; + }; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_reg_1v8: reg-1v8-grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 /* COM pin 144 */ + MX8MP_DSE_X1 + >; + }; + + pinctrl_reg_5v0_sensor: reg-5v0-sensorgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 /* COM pin 108 */ + MX8MP_DSE_X1 + >; + }; + + pinctrl_tas_reset: tasresetgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 /* COM pin 143 */ + MX8MP_DSE_X1 + >; + }; + + pinctrl_bt: btgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 /* COM pin 27 */ + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 /* COM pin 34 */ + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 /* COM pin 28 */ + MX8MP_DSE_X1 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI /* COM pin 46 */ + MX8MP_DSE_X4 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO /* COM pin 47 */ + (MX8MP_DSE_X4 | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK /* COM pin 48 */ + MX8MP_DSE_X4 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 /* COM pin 51 */ + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 /* COM pin 162 */ + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 /* COM pin 161 */ + MX8MP_DSE_X1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX /* COM pin 81 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX /* COM pin 76 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 /* COM pin 101 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART3_TXD__CAN2_RX /* COM pin 61 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART3_RXD__CAN2_TX /* COM pin 62 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 /* COM pin 44 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL /* COM pin 41 */ + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA /* COM pin 40 */ + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 /* COM pin 41 */ + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 /* COM pin 40 */ + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL /* COM pin 70 */ + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA /* COM pin 69 */ + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 /* COM pin 70 */ + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 /* COM pin 69 */ + (MX8MP_DSE_X4 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE |= MX8MP_SION) + >; + }; + + pinctrl_sai6: sai6grp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC /* COM pin 95 */ + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK /* COM pin 105 */ + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 /* COM pin 110 */ + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK /* COM pin 96 */ + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT) + MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 /* COM pin 106 */ + (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT) + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX /* COM pin 60 */ + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX /* COM pin 59 */ + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX /* COM pin 64 */ + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX /* COM pin 63 */ + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS /* COM pin 65 */ + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS /* COM pin 66 */ + (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_usdhc2: pinctrlusdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK /* COM pin 57 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_ENABLE) + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD /* COM pin 56 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 /* COM pin 52 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 /* COM pin 53 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 /* COM pin 54 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 /* COM pin 55 */ + (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | M= X8MP_PULL_ENABLE) + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B /* COM pin 153 */ + (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_HYS_SCHMITT) + >; + }; + + pinctrl_wl_int: wlintgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 /* COM pin 36 */ + (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) + >; + }; + + pinctrl_wl_reg: wlreggrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 /* COM pin 15 */ + MX8MP_DSE_X1 + >; + }; +}; --=20 2.49.0 From nobody Wed Dec 17 08:54:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E73631A0BD6; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743090760; cv=none; b=WicnVxwWarfaOaQHyhYLp1B36MAFEg8UuOUo3FCJdh4NSmB8Lf7JC7zW1dZ0hPpCQNWyIpKvQud6ltEhcyAQXU4bvaBZNxxFsBS6A8r06lS2Pivk9S4oCHbgjsAF23/oSiTkMpZM8L3+Lboui3y3YcnnVqkoT/8K+ncbHta1B7s= ARC-Message-Signature: i=1; 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b=o5EaS9AVobNdejiUNROqnpNAo98LS9GeRC4bx8lTx2Q55rsK7lkWo/zeToccefmF1 3ENAiDU7D5bwJIpLGXf+DQNO3rW4c7IJ9N8Xoye00MpVkrgpXRHXAsCooVxeLQHlDs MVRbROcEGpWcWiMCm6NQpG8uU6G6dCSQyukOaXGNwqz9+8eVoRQ60E5fS2WCGLur+/ 956wtsxYft/gjSJKXwoAJXchV/hvONikvH4cIB/EvWglNLOVpPSyc9VjMXWJvX2Wc4 ABibHeTFkAZ9XaSHOaY7hHatDLCb+bzGRlxbMjGR1ZNjWD/UboBAR2S05do/ktgzRz Ar0/5G2DBuvSw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A9F2C36011; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) From: Maud Spierings via B4 Relay Date: Thu, 27 Mar 2025 16:52:42 +0100 Subject: [PATCH v3 7/8] arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-7-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=3190; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=9JsvZTh+jeRunr4jwSFH14Q7W1rkRvW/yMNW6oZgbRA=; b=7fVRYA7EtUaSt65eRTx5ZTYZdQw7B89AExlyQNxaJfW1Lz/8RyUmgHlALufUAT0QLW2agbGBt qxV3/eLTlpADqOGL4JBIrTYbzZDX7EvJ7aLiyxsRgK1h0Qh1Ar683XD X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add the BOE av101hdt-a10 variant of the Moduline Display, this variant comes with a 10.1 1280x720 display with a touchscreen (not working in mainline). Signed-off-by: Maud Spierings --- Currently the backlight driver is not available, this will be upstreamed in a future patch series. It is a Maxim max25014atg. The touchscreen has a Cypress CYAT81658-64AS48 controller which as far as I know is not supported upstream, the driver we currently use for this is a mess and I doubt we will be able to get it in an upstreamable state. --- ...tx8p-ml81-moduline-display-106-av101hdt-a10.dts | 100 +++++++++++++++++= ++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-displa= y-106-av101hdt-a10.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-mod= uline-display-106-av101hdt-a10.dts new file mode 100644 index 0000000000000000000000000000000000000000..1917e22001a1815a6540f00cf03= 9ff352801cda8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-a= v101hdt-a10.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2025 GOcontroll B.V. + * Author: Maud Spierings + */ + +/dts-v1/; + +#include "imx8mp-tx8p-ml81-moduline-display-106.dtsi" + +/ { + model =3D "GOcontroll Moduline Display with BOE av101hdt-a10 display"; + + panel { + compatible =3D "boe,av101hdt-a10"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel>; + enable-gpios =3D <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio1 9 GPIO_ACTIVE_LOW>; + power-supply =3D <®_3v3_per>; + + port { + panel_lvds_in: endpoint { + remote-endpoint =3D <&ldb_lvds_ch0>; + }; + }; + }; + + reg_vbus: regulator-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-c-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + power-supply =3D <®_6v4>; + regulator-always-on; + }; +}; + +&lcdif2 { + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb3_phy1 { + status =3D "okay"; +}; + +&usb_dwc3_1 { + dr_mode =3D "host"; + + port { + usb1_hs_ep: endpoint { + remote-endpoint =3D <&high_speed_ep>; + }; + }; + + connector { + compatible =3D "usb-c-connector"; + pd-disable; + data-role =3D "host"; + vbus-supply =3D <®_vbus>; + + port { + high_speed_ep: endpoint { + remote-endpoint =3D <&usb1_hs_ep>; + }; + }; + }; +}; + +&lvds_bridge { + assigned-clocks =3D <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents =3D <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 =3D IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates =3D <0>, <1054620000>; + status =3D "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint =3D <&panel_lvds_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_panel: panelgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 /* COM pin 157 */ + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 /* COM pin 159 */ + MX8MP_DSE_X1 + >; + }; +}; --=20 2.49.0 From nobody Wed Dec 17 08:54:26 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E25221A08B5; Thu, 27 Mar 2025 15:52:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-initial_display-v3-8-4e89ea1676ab@gocontroll.com> References: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> In-Reply-To: <20250327-initial_display-v3-0-4e89ea1676ab@gocontroll.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Maud Spierings X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1743090757; l=3566; i=maudspierings@gocontroll.com; s=20250214; h=from:subject:message-id; bh=YMjOUoNCYJh9lEvif2+fl8SJFUv1GDzRxvcU2IcAvY0=; b=l8OXEChyuymPHCHLpQr47DGGXr4dN6ex5G3Zrf00MjXETLsbn9aih6VmJnTSr33lqYUyWHQAd rqnj7gb9UzQBagPTwWgzNl4tpuuihBOG/Ump39bOHxEF1MXsCqZfnhs X-Developer-Key: i=maudspierings@gocontroll.com; a=ed25519; pk=7chUb8XpaTQDvWhzTdHC0YPMkTDloELEC7q94tOUyPg= X-Endpoint-Received: by B4 Relay for maudspierings@gocontroll.com/20250214 with auth_id=341 X-Original-From: Maud Spierings Reply-To: maudspierings@gocontroll.com From: Maud Spierings Add the BOE av123z7m-n17 variant of the Moduline Display, this variant comes with a 12.3" 1920x720 display. Signed-off-by: Maud Spierings --- Currently the backlight driver is not available, this will be upstreamed in a future patch series. It is a Maxim max25014atg. --- ...tx8p-ml81-moduline-display-106-av123z7m-n17.dts | 133 +++++++++++++++++= ++++ 1 file changed, 133 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-displa= y-106-av123z7m-n17.dts b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-mod= uline-display-106-av123z7m-n17.dts new file mode 100644 index 0000000000000000000000000000000000000000..129c69598f38566460efb271628= c1d1e10eb2a85 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106-a= v123z7m-n17.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2025 GOcontroll B.V. + * Author: Maud Spierings + */ + +/dts-v1/; + +#include "imx8mp-tx8p-ml81-moduline-display-106.dtsi" + +/ { + model =3D "GOcontroll Moduline Display with BOE av123z7m-n17 display"; + + panel { + compatible =3D "boe,av123z7m-n17"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel>; + enable-gpios =3D <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&gpio1 9 GPIO_ACTIVE_LOW>; + power-supply =3D <®_3v3_per>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dual-lvds-odd-pixels; + + panel_in0: endpoint { + remote-endpoint =3D <&lvds1_out>; + }; + }; + + port@1 { + reg =3D <1>; + dual-lvds-even-pixels; + + panel_in1: endpoint { + remote-endpoint =3D <&lvds0_out>; + }; + }; + }; + }; +}; + +&i2c4 { + bridge@2d { /* sn65dsi85 */ + compatible =3D "ti,sn65dsi84"; + reg =3D <0x2d>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_lvds_bridge>; + enable-gpios =3D <&gpio4 14 GPIO_ACTIVE_HIGH>; + vcc-supply =3D <®_1v8_per>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint =3D <&mipi_dsi_out>; + data-lanes =3D <1 2 3 4>; + }; + }; + + port@2 { + reg =3D <2>; + + lvds0_out: endpoint { + remote-endpoint =3D <&panel_in1>; + }; + }; + + port@3 { + reg =3D <3>; + + lvds1_out: endpoint { + remote-endpoint =3D <&panel_in0>; + }; + }; + }; + }; + + /* max25014 @ 0x6f */ +}; + +&lcdif1 { + status =3D "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency =3D <12000000>; + /* + * burst has to be at least 2x dsi clock that the sn65dsi85 expects + * display pixelclock * bpp / lanes / 2 =3D dsi clock + * 88.000.000 * 24 / 4 / 2 =3D 264.000.000 + * range gets rounded up to 265.000.000 - 270.000.000 + * 267.500.000 * 2 =3D 535.000.000 + */ + samsung,burst-clock-frequency =3D <535000000>; + status =3D "okay"; + + ports { + port@1 { + mipi_dsi_out: endpoint { + remote-endpoint =3D < &dsi_lvds_bridge_in>; + data-lanes =3D <1 2 3 4>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lvds_bridge: lvdsbridgegrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 /* COM pin 113 */ + MX8MP_DSE_X1 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 /* COM pin 157 */ + MX8MP_DSE_X1 + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 /* COM pin 159 */ + MX8MP_DSE_X1 + >; + }; +}; --=20 2.49.0