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Thu, 27 Mar 2025 12:36:19 -0700 (PDT) From: Atish Patra Date: Thu, 27 Mar 2025 12:35:46 -0700 Subject: [PATCH v5 05/21] RISC-V: Define indirect CSR access helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250327-counter_delegation-v5-5-1ee538468d1b@rivosinc.com> References: <20250327-counter_delegation-v5-0-1ee538468d1b@rivosinc.com> In-Reply-To: <20250327-counter_delegation-v5-0-1ee538468d1b@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 The indriect CSR requires multiple instructions to read/write CSR. Add a few helper functions for ease of usage. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr_ind.h | 42 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_= ind.h new file mode 100644 index 000000000000..d36e1e06ed2b --- /dev/null +++ b/arch/riscv/include/asm/csr_ind.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 Rivos Inc. + */ + +#ifndef _ASM_RISCV_CSR_IND_H +#define _ASM_RISCV_CSR_IND_H + +#include + +#define csr_ind_read(iregcsr, iselbase, iseloff) ({ \ + unsigned long value =3D 0; \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + value =3D csr_read(iregcsr); \ + local_irq_restore(flags); \ + value; \ +}) + +#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({ \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + csr_write(iregcsr, value); \ + local_irq_restore(flags); \ +}) + +#define csr_ind_warl(iregcsr, iselbase, iseloff, warl_val) ({ \ + unsigned long old_val =3D 0, value =3D 0; \ + unsigned long flags; \ + local_irq_save(flags); \ + csr_write(CSR_ISELECT, iselbase + iseloff); \ + old_val =3D csr_read(iregcsr); \ + csr_write(iregcsr, warl_val); \ + value =3D csr_read(iregcsr); \ + csr_write(iregcsr, old_val); \ + local_irq_restore(flags); \ + value; \ +}) + +#endif --=20 2.43.0