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<20250327-counter_delegation-v5-0-1ee538468d1b@rivosinc.com> In-Reply-To: <20250327-counter_delegation-v5-0-1ee538468d1b@rivosinc.com> To: Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Atish Patra X-Mailer: b4 0.15-dev-42535 Signed-off-by: Atish Patra --- tools/perf/pmu-events/empty-pmu-events.c | 144 +++++++++++++++------------= ---- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-even= ts/empty-pmu-events.c index 3a7ec31576f5..22f0463dc522 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -36,42 +36,42 @@ static const char *const big_c_string =3D /* offset=3D1127 */ "bp_l1_btb_correct\000branch\000L1 BTB Correction\000e= vent=3D0x8a\000\00000\000\000\000" /* offset=3D1187 */ "bp_l2_btb_correct\000branch\000L2 BTB Correction\000e= vent=3D0x8b\000\00000\000\000\000" /* offset=3D1247 */ "l3_cache_rd\000cache\000L3 cache access, read\000even= t=3D0x40\000\00000\000Attributable Level 3 cache access, read\000\000" -/* offset=3D1343 */ "segment_reg_loads.any\000other\000Number of segment r= egister loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\0000,= 1\000" -/* offset=3D1446 */ "dispatch_blocked.any\000other\000Memory cluster signa= ls to block micro-op dispatch for any reason\000event=3D9,period=3D200000,u= mask=3D0x20\000\00000\000\0000,1\000" -/* offset=3D1580 */ "eist_trans\000other\000Number of Enhanced Intel Speed= Step(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\0= 0000\000\0000,1\000" -/* offset=3D1699 */ "hisi_sccl,ddrc\000" -/* offset=3D1714 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write co= mmands\000event=3D2\000\00000\000DDRC write commands\000\000" -/* offset=3D1801 */ "uncore_cbox\000" -/* offset=3D1813 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cr= oss-core snoop resulted from L3 Eviction which misses in some processor cor= e\000event=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted fro= m L3 Eviction which misses in some processor core\0000,1\000" -/* offset=3D2048 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0= xe0\000\00000\000UNC_CBO_HYPHEN\000\000" -/* offset=3D2114 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event= =3D0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" -/* offset=3D2186 */ "hisi_sccl,l3c\000" -/* offset=3D2200 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read = hits\000event=3D7\000\00000\000Total read hits\000\000" -/* offset=3D2281 */ "uncore_imc_free_running\000" -/* offset=3D2305 */ "uncore_imc_free_running.cache_miss\000uncore\000Total= cache misses\000event=3D0x12\000\00000\000Total cache misses\000\000" -/* offset=3D2401 */ "uncore_imc\000" -/* offset=3D2412 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\0= 00event=3D0x34\000\00000\000Total cache hits\000\000" -/* offset=3D2491 */ "uncore_sys_ddr_pmu\000" -/* offset=3D2510 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycle= s event\000event=3D0x2b\000v8\00000\000\000\000" -/* offset=3D2584 */ "uncore_sys_ccn_pmu\000" -/* offset=3D2603 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles = event\000config=3D0x2c\0000x01\00000\000\000\000" -/* offset=3D2678 */ "uncore_sys_cmn_pmu\000" -/* offset=3D2697 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total = cache misses in first lookup result (high priority)\000eventid=3D1,type=3D5= \000(434|436|43c|43a).*\00000\000\000\000" -/* offset=3D2838 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" -/* offset=3D2860 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.= thread\000\000\000\000\000\000\000\00000" -/* offset=3D2923 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core= / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_act= ive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" -/* offset=3D3089 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_re= tired.any\000\000\000\000\000\000\000\00000" -/* offset=3D3153 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst= _retired.any\000\000\000\000\000\000\000\00000" -/* offset=3D3220 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icac= he_miss_cycles\000\000\000\000\000\000\000\00000" -/* offset=3D3291 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit= + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" -/* offset=3D3385 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_dat= a_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_mi= ss\000\000\000\000\000\000\000\00000" -/* offset=3D3519 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_A= ll_Miss\000\000\000\000\000\000\000\00000" -/* offset=3D3583 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCa= che_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D3651 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" -/* offset=3D3721 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" -/* offset=3D3743 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" -/* offset=3D3765 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" -/* offset=3D3785 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 /= duration_time\000\000\000\000\000\000\000\00000" +/* offset=3D1343 */ "segment_reg_loads.any\000other\000Number of segment r= egister loads\000event=3D6,period=3D200000,umask=3D0x80,counterid_mask=3D0x= 3\000\00000\000\0000,1\000" +/* offset=3D1465 */ "dispatch_blocked.any\000other\000Memory cluster signa= ls to block micro-op dispatch for any reason\000event=3D9,period=3D200000,u= mask=3D0x20,counterid_mask=3D0x3\000\00000\000\0000,1\000" +/* offset=3D1618 */ "eist_trans\000other\000Number of Enhanced Intel Speed= Step(R) Technology (EIST) transitions\000event=3D0x3a,period=3D200000,count= erid_mask=3D0x3\000\00000\000\0000,1\000" +/* offset=3D1756 */ "hisi_sccl,ddrc\000" +/* offset=3D1771 */ "uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write co= mmands\000event=3D2\000\00000\000DDRC write commands\000\000" +/* offset=3D1858 */ "uncore_cbox\000" +/* offset=3D1870 */ "unc_cbo_xsnp_response.miss_eviction\000uncore\000A cr= oss-core snoop resulted from L3 Eviction which misses in some processor cor= e\000event=3D0x22,umask=3D0x81,counterid_mask=3D0x3\000\00000\000A cross-co= re snoop resulted from L3 Eviction which misses in some processor core\0000= ,1\000" +/* offset=3D2124 */ "event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0= xe0\000\00000\000UNC_CBO_HYPHEN\000\000" +/* offset=3D2190 */ "event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event= =3D0xc0\000\00000\000UNC_CBO_TWO_HYPH\000\000" +/* offset=3D2262 */ "hisi_sccl,l3c\000" +/* offset=3D2276 */ "uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read = hits\000event=3D7\000\00000\000Total read hits\000\000" +/* offset=3D2357 */ "uncore_imc_free_running\000" +/* offset=3D2381 */ "uncore_imc_free_running.cache_miss\000uncore\000Total= cache misses\000event=3D0x12\000\00000\000Total cache misses\000\000" +/* offset=3D2477 */ "uncore_imc\000" +/* offset=3D2488 */ "uncore_imc.cache_hits\000uncore\000Total cache hits\0= 00event=3D0x34\000\00000\000Total cache hits\000\000" +/* offset=3D2567 */ "uncore_sys_ddr_pmu\000" +/* offset=3D2586 */ "sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycle= s event\000event=3D0x2b\000v8\00000\000\000\000" +/* offset=3D2660 */ "uncore_sys_ccn_pmu\000" +/* offset=3D2679 */ "sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles = event\000config=3D0x2c\0000x01\00000\000\000\000" +/* offset=3D2754 */ "uncore_sys_cmn_pmu\000" +/* offset=3D2773 */ "sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total = cache misses in first lookup result (high priority)\000eventid=3D1,type=3D5= \000(434|436|43c|43a).*\00000\000\000\000" +/* offset=3D2914 */ "CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000" +/* offset=3D2936 */ "IPC\000group1\000inst_retired.any / cpu_clk_unhalted.= thread\000\000\000\000\000\000\000\00000" +/* offset=3D2999 */ "Frontend_Bound_SMT\000\000idq_uops_not_delivered.core= / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_act= ive / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000" +/* offset=3D3165 */ "dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_re= tired.any\000\000\000\000\000\000\000\00000" +/* offset=3D3229 */ "icache_miss_cycles\000\000l1i\\-loads\\-misses / inst= _retired.any\000\000\000\000\000\000\000\00000" +/* offset=3D3296 */ "cache_miss_cycles\000group1\000dcache_miss_cpi + icac= he_miss_cycles\000\000\000\000\000\000\000\00000" +/* offset=3D3367 */ "DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit= + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000" +/* offset=3D3461 */ "DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_dat= a_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_mi= ss\000\000\000\000\000\000\000\00000" +/* offset=3D3595 */ "DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_A= ll_Miss\000\000\000\000\000\000\000\00000" +/* offset=3D3659 */ "DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCa= che_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D3727 */ "DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, D= Cache_L2_All)\000\000\000\000\000\000\000\00000" +/* offset=3D3797 */ "M1\000\000ipc + M2\000\000\000\000\000\000\000\00000" +/* offset=3D3819 */ "M2\000\000ipc + M1\000\000\000\000\000\000\000\00000" +/* offset=3D3841 */ "M3\000\0001 / M3\000\000\000\000\000\000\000\00000" +/* offset=3D3861 */ "L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 /= duration_time\000\000\000\000\000\000\000\00000" ; =20 static const struct compact_pmu_event pmu_events__common_tool[] =3D { @@ -101,27 +101,27 @@ const struct pmu_table_entry pmu_events__common[] =3D= { static const struct compact_pmu_event pmu_events__test_soc_cpu_default_cor= e[] =3D { { 1127 }, /* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=3D0= x8a\000\00000\000\000\000 */ { 1187 }, /* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=3D0= x8b\000\00000\000\000\000 */ -{ 1446 }, /* dispatch_blocked.any\000other\000Memory cluster signals to bl= ock micro-op dispatch for any reason\000event=3D9,period=3D200000,umask=3D0= x20\000\00000\000\0000,1\000 */ -{ 1580 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) = Technology (EIST) transitions\000event=3D0x3a,period=3D200000\000\00000\000= \0000,1\000 */ +{ 1465 }, /* dispatch_blocked.any\000other\000Memory cluster signals to bl= ock micro-op dispatch for any reason\000event=3D9,period=3D200000,umask=3D0= x20,counterid_mask=3D0x3\000\00000\000\0000,1\000 */ +{ 1618 }, /* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) = Technology (EIST) transitions\000event=3D0x3a,period=3D200000,counterid_mas= k=3D0x3\000\00000\000\0000,1\000 */ { 1247 }, /* l3_cache_rd\000cache\000L3 cache access, read\000event=3D0x40= \000\00000\000Attributable Level 3 cache access, read\000\000 */ -{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register = loads\000event=3D6,period=3D200000,umask=3D0x80\000\00000\000\0000,1\000 */ +{ 1343 }, /* segment_reg_loads.any\000other\000Number of segment register = loads\000event=3D6,period=3D200000,umask=3D0x80,counterid_mask=3D0x3\000\00= 000\000\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_d= drc[] =3D { -{ 1714 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\0= 00event=3D2\000\00000\000DDRC write commands\000\000 */ +{ 1771 }, /* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\0= 00event=3D2\000\00000\000DDRC write commands\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l= 3c[] =3D { -{ 2200 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000= event=3D7\000\00000\000Total read hits\000\000 */ +{ 2276 }, /* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000= event=3D7\000\00000\000Total read hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox= [] =3D { -{ 2048 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\= 00000\000UNC_CBO_HYPHEN\000\000 */ -{ 2114 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\= 000\00000\000UNC_CBO_TWO_HYPH\000\000 */ -{ 1813 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core= snoop resulted from L3 Eviction which misses in some processor core\000eve= nt=3D0x22,umask=3D0x81\000\00000\000A cross-core snoop resulted from L3 Evi= ction which misses in some processor core\0000,1\000 */ +{ 2124 }, /* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=3D0xe0\000\= 00000\000UNC_CBO_HYPHEN\000\000 */ +{ 2190 }, /* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=3D0xc0\= 000\00000\000UNC_CBO_TWO_HYPH\000\000 */ +{ 1870 }, /* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core= snoop resulted from L3 Eviction which misses in some processor core\000eve= nt=3D0x22,umask=3D0x81,counterid_mask=3D0x3\000\00000\000A cross-core snoop= resulted from L3 Eviction which misses in some processor core\0000,1\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[= ] =3D { -{ 2412 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event= =3D0x34\000\00000\000Total cache hits\000\000 */ +{ 2488 }, /* uncore_imc.cache_hits\000uncore\000Total cache hits\000event= =3D0x34\000\00000\000Total cache hits\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_= free_running[] =3D { -{ 2305 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache m= isses\000event=3D0x12\000\00000\000Total cache misses\000\000 */ +{ 2381 }, /* uncore_imc_free_running.cache_miss\000uncore\000Total cache m= isses\000event=3D0x12\000\00000\000Total cache misses\000\000 */ =20 }; =20 @@ -134,46 +134,46 @@ const struct pmu_table_entry pmu_events__test_soc_cpu= [] =3D { { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_ddrc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc), - .pmu_name =3D { 1699 /* hisi_sccl,ddrc\000 */ }, + .pmu_name =3D { 1756 /* hisi_sccl,ddrc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_hisi_sccl_l3c, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c), - .pmu_name =3D { 2186 /* hisi_sccl,l3c\000 */ }, + .pmu_name =3D { 2262 /* hisi_sccl,l3c\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_cbox, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox), - .pmu_name =3D { 1801 /* uncore_cbox\000 */ }, + .pmu_name =3D { 1858 /* uncore_cbox\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc), - .pmu_name =3D { 2401 /* uncore_imc\000 */ }, + .pmu_name =3D { 2477 /* uncore_imc\000 */ }, }, { .entries =3D pmu_events__test_soc_cpu_uncore_imc_free_running, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_= running), - .pmu_name =3D { 2281 /* uncore_imc_free_running\000 */ }, + .pmu_name =3D { 2357 /* uncore_imc_free_running\000 */ }, }, }; =20 static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_co= re[] =3D { -{ 2838 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ -{ 3519 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\= 000\000\000\000\000\000\000\00000 */ -{ 3291 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rq= sts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ -{ 3385 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l= 2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\0= 00\000\000\000\000\000\00000 */ -{ 3583 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_A= ll)\000\000\000\000\000\000\000\00000 */ -{ 3651 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ -{ 2923 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * = (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cp= u_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ -{ 2860 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\0= 00\000\000\000\000\000\000\00000 */ -{ 3785 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duratio= n_time\000\000\000\000\000\000\000\00000 */ -{ 3721 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ -{ 3743 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ -{ 3765 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ -{ 3220 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_= cycles\000\000\000\000\000\000\000\00000 */ -{ 3089 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.an= y\000\000\000\000\000\000\000\00000 */ -{ 3153 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired= .any\000\000\000\000\000\000\000\00000 */ +{ 2914 }, /* CPI\000\0001 / IPC\000\000\000\000\000\000\000\00000 */ +{ 3595 }, /* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\= 000\000\000\000\000\000\000\00000 */ +{ 3367 }, /* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rq= sts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\00000 */ +{ 3461 }, /* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l= 2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\0= 00\000\000\000\000\000\00000 */ +{ 3659 }, /* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_A= ll)\000\000\000\000\000\000\000\00000 */ +{ 3727 }, /* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2= _All)\000\000\000\000\000\000\000\00000 */ +{ 2999 }, /* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * = (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cp= u_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\00000 */ +{ 2936 }, /* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\0= 00\000\000\000\000\000\000\00000 */ +{ 3861 }, /* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duratio= n_time\000\000\000\000\000\000\000\00000 */ +{ 3797 }, /* M1\000\000ipc + M2\000\000\000\000\000\000\000\00000 */ +{ 3819 }, /* M2\000\000ipc + M1\000\000\000\000\000\000\000\00000 */ +{ 3841 }, /* M3\000\0001 / M3\000\000\000\000\000\000\000\00000 */ +{ 3296 }, /* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_= cycles\000\000\000\000\000\000\000\00000 */ +{ 3165 }, /* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.an= y\000\000\000\000\000\000\000\00000 */ +{ 3229 }, /* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired= .any\000\000\000\000\000\000\000\00000 */ =20 }; =20 @@ -186,13 +186,13 @@ const struct pmu_table_entry pmu_metrics__test_soc_cp= u[] =3D { }; =20 static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ccn_pmu[] =3D { -{ 2603 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\00= 0config=3D0x2c\0000x01\00000\000\000\000 */ +{ 2679 }, /* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\00= 0config=3D0x2c\0000x01\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= cmn_pmu[] =3D { -{ 2697 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache mi= sses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(434= |436|43c|43a).*\00000\000\000\000 */ +{ 2773 }, /* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache mi= sses in first lookup result (high priority)\000eventid=3D1,type=3D5\000(434= |436|43c|43a).*\00000\000\000\000 */ }; static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_= ddr_pmu[] =3D { -{ 2510 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\= 000event=3D0x2b\000v8\00000\000\000\000 */ +{ 2586 }, /* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\= 000event=3D0x2b\000v8\00000\000\000\000 */ =20 }; =20 @@ -200,17 +200,17 @@ const struct pmu_table_entry pmu_events__test_soc_sys= [] =3D { { .entries =3D pmu_events__test_soc_sys_uncore_sys_ccn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_p= mu), - .pmu_name =3D { 2584 /* uncore_sys_ccn_pmu\000 */ }, + .pmu_name =3D { 2660 /* uncore_sys_ccn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_cmn_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_p= mu), - .pmu_name =3D { 2678 /* uncore_sys_cmn_pmu\000 */ }, + .pmu_name =3D { 2754 /* uncore_sys_cmn_pmu\000 */ }, }, { .entries =3D pmu_events__test_soc_sys_uncore_sys_ddr_pmu, .num_entries =3D ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_p= mu), - .pmu_name =3D { 2491 /* uncore_sys_ddr_pmu\000 */ }, + .pmu_name =3D { 2567 /* uncore_sys_ddr_pmu\000 */ }, }, }; =20 --=20 2.43.0