From nobody Wed Dec 17 07:10:51 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C0A81FE45D for ; Wed, 26 Mar 2025 15:37:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003473; cv=none; b=BVWYrc7Efxa2NL64LvMB+k2ZSx68No85z0EA+kcCitilpwsKR8f0kTP9N/w78OIc9coMCeK/lG8Zz3J873fXEArPCgkpawOR99A83cp6LwNeulNERvQKJ3KjzSxz62zQ85NyJI2/AGfAkO7OJ7R9AbLBtwlnKPr7y7yZRMtb6rQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743003473; c=relaxed/simple; bh=02tjDKQNWeXHFLJTCMQ3g4lvV4tJ61jI02p0lATS/lk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kkci5C0SLIJomJldjJXI++vuDuQ2mwNdk6OCNJxsvdtC1P+lVItQ19FD5I9KL1iahPpqZw7Gr+5gwRe+UdGzsx+fyWIGGBANqEBDAJwg3AEIAhQA6iQ9c9SC8j8ZK1afxLPQVBgHc3kkBFYuvnq2D92tS9TiY2UKcI5p5GdgZQo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iE8sTpCo; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iE8sTpCo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743003472; x=1774539472; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=02tjDKQNWeXHFLJTCMQ3g4lvV4tJ61jI02p0lATS/lk=; b=iE8sTpCoQ8tcY52LDDMdVX+NSYgq5LZOTPtBTMQfydkijA70Udj44ejB qiUELY5Jnia95Vkg84rz1tDDACT8879ulnWhww8mMao46AV9OU7GyPqj9 iJFyA6J3dXtMw6mIqFkHHHHdPitHZbXRuLVtwsxmGvK6XBtOkJ8pzCyD0 StHUZdUpXAdSGS26fhryQBA+JnRIAFEcKGJZAx7WC+1H5bRa11aL8bIHg zuplFme5Wsh93bYPnH6VyIFsE+WWpwJnm7yXtNWh5MFnz0czVVlZfIQcm 85AJaKqhwSkiAYhED8Umq/+Fjgs/MzJChqfFWzv0Vte9eSV+li9J+VDvH g==; X-CSE-ConnectionGUID: YmMJj7XdQOasLFBfG3e9gw== X-CSE-MsgGUID: jIeJaDE4R/aykAHkvIBgBw== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="55665519" X-IronPort-AV: E=Sophos;i="6.14,278,1736841600"; d="scan'208";a="55665519" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 08:37:52 -0700 X-CSE-ConnectionGUID: y5VlznP4Qtyq8zC7+2hq6w== X-CSE-MsgGUID: pyccQ9ogRCy32+LBHrYCng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,278,1736841600"; d="scan'208";a="129923501" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 08:37:46 -0700 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa Cc: Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v7 06/12] mtd: intel-dg: align 64bit read and write Date: Wed, 26 Mar 2025 17:26:17 +0200 Message-ID: <20250326152623.3897204-7-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250326152623.3897204-1-alexander.usyskin@intel.com> References: <20250326152623.3897204-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GSC NVM controller HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border. Acked-by: Miquel Raynal Signed-off-by: Alexander Usyskin --- drivers/mtd/devices/mtd_intel_dg.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_i= ntel_dg.c index 4023f2ebc344..3535f7b64429 100644 --- a/drivers/mtd/devices/mtd_intel_dg.c +++ b/drivers/mtd/devices/mtd_intel_dg.c @@ -238,6 +238,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 = region, len_s -=3D to_shift; } =20 + if (!IS_ALIGNED(to, sizeof(u64)) && + ((to ^ (to + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data; + + memcpy(&data, &buf[0], sizeof(u32)); + idg_nvm_write32(nvm, to, data); + if (idg_nvm_error(nvm)) + return -EIO; + buf +=3D sizeof(u32); + to +=3D sizeof(u32); + len_s -=3D sizeof(u32); + } + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); for (i =3D 0; i < len8; i +=3D sizeof(u64)) { u64 data; @@ -295,6 +313,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 r= egion, from +=3D from_shift; } =20 + if (!IS_ALIGNED(from, sizeof(u64)) && + ((from ^ (from + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data =3D idg_nvm_read32(nvm, from); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[0], &data, sizeof(data)); + len_s -=3D sizeof(u32); + buf +=3D sizeof(u32); + from +=3D sizeof(u32); + } + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); for (i =3D 0; i < len8; i +=3D sizeof(u64)) { u64 data =3D idg_nvm_read64(nvm, from + i); --=20 2.43.0