From nobody Wed Dec 17 05:28:27 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8D17153BE8 for ; Wed, 26 Mar 2025 15:23:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743002617; cv=none; b=JRNGB27eByTfc7OFgpdOZ7mF1R6qv/kGuoXEieFt5D8vkKUMnLPUt0PpML3pz5A+ddGu8GqWN8w9Di4Ww/0R168FlX1qaqnuCfp0uv60Iu2iCImmbgu6UqAb4PG5k491V8xkn4W7CaVK/WH0ge9Yemk8yQbmBkaJXxv3Zolph6M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743002617; c=relaxed/simple; bh=LTuJihWWgilndmk9mTgn3jlXLSh19OZ/HAUZDX0/VUk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lP+p2GQw0NgrKzxv0IBM5vPxj2bjyLhohy3aE/yw08NGe18xkqLLaNioSzxAqLc5CkLMCbiwUdEU9dPOTuCF3sls0BxsOOaYTqQFePt8nqj8fSJHCdrBeL6akcDXTQ7zxlP0H/v3WmncWNY571RNg2zzwA3cdXSiliY6O7VnKyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ZfyXjtOv; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ZfyXjtOv" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 52QFNN5o2128035 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 26 Mar 2025 10:23:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743002603; bh=HYIha5KWB07+PC+ckhBYmLlo27ya2SY+HumbYnoxom4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZfyXjtOvkoqMCIG4TYPcSaua7z4sSGfhavxsdwpJmD/6Ft5RcU6i84U5vkFK2Apis qF4LDaFVr4UmAaydcvtXy8q3XLOWkxGGZGEIoOZXfWmVm0HY41YX8WSztWNKfkCMwP vcM33Wu4NPyVDeF08r+Q51Nmx9ckX9XT6A1OKyDo= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 52QFNNGg125628; Wed, 26 Mar 2025 10:23:23 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 26 Mar 2025 10:23:22 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Mar 2025 10:23:22 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 52QFNMfH076834; Wed, 26 Mar 2025 10:23:22 -0500 From: Devarsh Thakkar To: , , , , CC: , , , , , , Subject: [PATCH v2 1/2] phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling Date: Wed, 26 Mar 2025 20:53:19 +0530 Message-ID: <20250326152320.3835249-2-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250326152320.3835249-1-devarsht@ti.com> References: <20250326152320.3835249-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" PLL lockup and O_CMN_READY assertion can only happen after common state machine gets enabled, but driver was polling them before the common state machine was enabled. To fix this, add new function callbacks polling on PLL lock and O_CMN_READY assertion and call them only after common state machine gets enabled. Cc: stable@vger.kernel.org Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") Signed-off-by: Devarsh Thakkar --- V2:=20 - Return error code on polling timeout - Moved out calibration logic to separate patch drivers/phy/cadence/cdns-dphy.c | 57 ++++++++++++++++++++++++++++----- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dph= y.c index ed87a3970f83..c4de9e4d3e93 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -99,6 +99,8 @@ struct cdns_dphy_ops { void (*set_pll_cfg)(struct cdns_dphy *dphy, const struct cdns_dphy_cfg *cfg); unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy); + int (*wait_for_pll_lock)(struct cdns_dphy *dphy); + int (*wait_for_cmn_ready)(struct cdns_dphy *dphy); }; =20 struct cdns_dphy { @@ -191,6 +193,26 @@ static unsigned long cdns_dphy_get_wakeup_time_ns(stru= ct cdns_dphy *dphy) return dphy->ops->get_wakeup_time_ns(dphy); } =20 +static int cdns_dphy_wait_for_pll_lock(struct cdns_dphy *dphy) +{ + int ret =3D 0; + + if (dphy->ops->wait_for_pll_lock) + ret =3D dphy->ops->wait_for_pll_lock(dphy); + + return ret; +} + +static int cdns_dphy_wait_for_cmn_ready(struct cdns_dphy *dphy) +{ + int ret =3D 0; + + if (dphy->ops->wait_for_cmn_ready) + ret =3D dphy->ops->wait_for_cmn_ready(dphy); + + return ret; +} + static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dp= hy) { /* Default wakeup time is 800 ns (in a simulated environment). */ @@ -232,7 +254,6 @@ static unsigned long cdns_dphy_j721e_get_wakeup_time_ns= (struct cdns_dphy *dphy) static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy *dphy, const struct cdns_dphy_cfg *cfg) { - u32 status; =20 /* * set the PWM and PLL Byteclk divider settings to recommended values @@ -249,13 +270,6 @@ static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dp= hy *dphy, =20 writel(DPHY_TX_J721E_WIZ_LANE_RSTB, dphy->regs + DPHY_TX_J721E_WIZ_RST_CTRL); - - readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status, - (status & DPHY_TX_WIZ_PLL_LOCK), 0, POLL_TIMEOUT_US); - - readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status, - (status & DPHY_TX_WIZ_O_CMN_READY), 0, - POLL_TIMEOUT_US); } =20 static void cdns_dphy_j721e_set_psm_div(struct cdns_dphy *dphy, u8 div) @@ -263,6 +277,23 @@ static void cdns_dphy_j721e_set_psm_div(struct cdns_dp= hy *dphy, u8 div) writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ); } =20 +static int cdns_dphy_j721e_wait_for_pll_lock(struct cdns_dphy *dphy) +{ + u32 status; + + return readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status, + status & DPHY_TX_WIZ_PLL_LOCK, 0, POLL_TIMEOUT_US); +} + +static int cdns_dphy_j721e_wait_for_cmn_ready(struct cdns_dphy *dphy) +{ + u32 status; + + return readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status, + status & DPHY_TX_WIZ_O_CMN_READY, 0, + POLL_TIMEOUT_US); +} + /* * This is the reference implementation of DPHY hooks. Specific integratio= n of * this IP may have to re-implement some of them depending on how they dec= ided @@ -278,6 +309,8 @@ static const struct cdns_dphy_ops j721e_dphy_ops =3D { .get_wakeup_time_ns =3D cdns_dphy_j721e_get_wakeup_time_ns, .set_pll_cfg =3D cdns_dphy_j721e_set_pll_cfg, .set_psm_div =3D cdns_dphy_j721e_set_psm_div, + .wait_for_pll_lock =3D cdns_dphy_j721e_wait_for_pll_lock, + .wait_for_cmn_ready =3D cdns_dphy_j721e_wait_for_cmn_ready, }; =20 static int cdns_dphy_config_from_opts(struct phy *phy, @@ -373,6 +406,14 @@ static int cdns_dphy_configure(struct phy *phy, union = phy_configure_opts *opts) FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); writel(reg, dphy->regs + DPHY_BAND_CFG); =20 + ret =3D cdns_dphy_wait_for_pll_lock(dphy); + if (ret) + dev_err(&dphy->phy->dev, "Failed to lock PLL with err %d\n", ret); + + ret =3D cdns_dphy_wait_for_cmn_ready(dphy); + if (ret) + dev_err(&dphy->phy->dev, "O_CMN_READY signal failed to assert with err %= d\n", ret); + return 0; } =20 --=20 2.39.1 From nobody Wed Dec 17 05:28:27 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45EFB1F4165 for ; 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Wed, 26 Mar 2025 10:23:24 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 26 Mar 2025 10:23:24 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 26 Mar 2025 10:23:24 -0500 Received: from localhost (ti.dhcp.ti.com [172.24.227.95] (may be forged)) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 52QFNNXW076869; Wed, 26 Mar 2025 10:23:23 -0500 From: Devarsh Thakkar To: , , , , CC: , , , , , , Subject: [PATCH v2 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine Date: Wed, 26 Mar 2025 20:53:20 +0530 Message-ID: <20250326152320.3835249-3-devarsht@ti.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20250326152320.3835249-1-devarsht@ti.com> References: <20250326152320.3835249-1-devarsht@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Use system characterized reset value specified in TRM [1] to program calibration wait time which defines number of cycles to wait for after startup state machine is in bandgap enable state. This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's AM62L and J721E SoC [2]. [1] AM62P TRM (Section ): https://www.ti.com/lit/pdf/spruj83 [2]: Link: https://gist.github.com/devarsht/89e4830e886774fcd50aa6e29cce3a79 Cc: stable@vger.kernel.org Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support") Signed-off-by: Devarsh Thakkar --- V2: Introduced this as as separate patch drivers/phy/cadence/cdns-dphy.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dph= y.c index c4de9e4d3e93..11fbffe5aafd 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -30,6 +30,7 @@ =20 #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) #define DPHY_CMN_SSM_EN BIT(0) +#define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1) #define DPHY_CMN_TX_MODE_EN BIT(9) =20 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) @@ -405,6 +406,8 @@ static int cdns_dphy_configure(struct phy *phy, union p= hy_configure_opts *opts) reg =3D FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); writel(reg, dphy->regs + DPHY_BAND_CFG); + writel(FIELD_PREP(DPHY_CMN_SSM_CAL_WAIT_TIME, 0x14) | DPHY_CMN_SSM_EN | D= PHY_CMN_TX_MODE_EN, + dphy->regs + DPHY_CMN_SSM); =20 ret =3D cdns_dphy_wait_for_pll_lock(dphy); if (ret) --=20 2.39.1