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Wed, 26 Mar 2025 16:49:02 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.0.133) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 16:48:53 +0000 From: Matt Coster Date: Wed, 26 Mar 2025 16:48:37 +0000 Subject: [PATCH DO NOT MERGE v5 17/18] arm64: dts: ti: k3-am62: New GPU binding details Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250326-sets-bxs-4-64-patch-v1-v5-17-e4c46e8280a9@imgtec.com> References: <20250326-sets-bxs-4-64-patch-v1-v5-0-e4c46e8280a9@imgtec.com> In-Reply-To: <20250326-sets-bxs-4-64-patch-v1-v5-0-e4c46e8280a9@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Michal Wilczynski" , Alessio Belle , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1705; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=AiV3JtqpuKX4w4TzhqQhNz5mqpYDAlaAlzR9okWvUas=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaQ/0X/2xFifk7voZ9WZxoMvSozkVxhGMSnNnxb12JFJ1 8POKUSgo5SFQYyDQVZMkWXHCssVan/UtCRu/CqGmcPKBDKEgYtTACZyci0jw/XG6W8dhX7Mn+Vk rakW/NEqiPta7dtLs9xUj8kuX3/pZgjDX6lzm9xsj4ccn3H65aYJFXNXGeedz9399OFzph2qCd0 bZ/ACAA== X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: U_OTcN-_xOCu4tQDDwLneFQVcMEy5-aR X-Authority-Analysis: v=2.4 cv=L+sdQ/T8 c=1 sm=1 tr=0 ts=67e42ffe cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=ETbM1kImDFEA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=OLj8r6_nq0VfqmG8xPEA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: U_OTcN-_xOCu4tQDDwLneFQVcMEy5-aR Use the new compatible string introduced earlier (in "dt-bindings: gpu: img: More explicit compatible strings") and add a name to the single power domain for this GPU (introduced in "dt-bindings: gpu: img: Power domain details"). Signed-off-by: Matt Coster --- Changes in v5: - None - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-= 17-d987cf4ca439@imgtec.com Changes in v4: - None - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-= 17-143b3dbef02f@imgtec.com Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-= 7-3fd45d9fb0cf@imgtec.com Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 7-4ed30e865892@imgtec.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 7d355aa73ea2116723735f70b9351cefcd8bc118..d17b25cae196b08d24adbe7c913= ccaba7eed37eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -691,12 +691,14 @@ ospi0: spi@fc40000 { }; =20 gpu: gpu@fd00000 { - compatible =3D "ti,am62-gpu", "img,img-axe"; + compatible =3D "ti,am62-gpu", "img,img-axe-1-16m", "img,img-axe", + "img,img-rogue"; reg =3D <0x00 0x0fd00000 0x00 0x20000>; clocks =3D <&k3_clks 187 0>; clock-names =3D "core"; interrupts =3D ; power-domains =3D <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a"; }; =20 cpsw3g: ethernet@8000000 { --=20 2.49.0