From nobody Fri Dec 19 14:10:39 2025 Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B01411FC0F3; Wed, 26 Mar 2025 16:49:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743007767; cv=none; b=aQv9hz1PEJuN6tTocAJqyQbeDAC8bJwJhO0lVd83bULZ0Jb/QLFbrWteK6koRvPuhWs/rIpbJ8Hom7Y4LkjJbIujM8NRB9/PJZvgbhT/5RTM4OeHDHOKa0wvlWq5QvHrGW+0gBiCXykC9c9AtKg/+JZ13A/Yx54Aq3E8NDn32GQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743007767; c=relaxed/simple; bh=AGBvIBv7eUE58QmH1vxKVNMYOVNCjNhYNw59cwAmh/o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=TEUf5F2EIN5jB3afOkNiPU2lIsCNM0+rxuxrtqCu9sHYZZAAFwCY/VHzOYctynKPrTsNr4MJyngCDlTyH4PAlsAiar1KLzp153KDRQCkUARkZm30DVm8Syb7bBHRtTaGyu/SlFh8D5vN6NlugFFKcFzkSQlHEsVIZCeSv/rQ8d4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=Ti1+oqFM; arc=none smtp.client-ip=91.207.212.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="Ti1+oqFM" Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52QBt2Sk012691; Wed, 26 Mar 2025 16:48:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=F A0lyH8FWOP6f5VYzns8OJMOqNymYsYVmZjrDckF4co=; b=Ti1+oqFM+luH1KI0g gu0mHq8MRFMu0P1wRR8QwOoTRmqFhdwG+3MsM1K03MHc10ZsRzDmuTPkv9Fr7S7e KcPAODQM4J5gmcK93i3DDJVZC1K1i+l0uCG3/MhAjHG/llD64oMNq6vH9C9yoiTJ DcnDjyHWB14cWUVUusS9+HEcG6RqjLRuRkO4LBvxkhhlSba2VICJgIoF0fDAZPx4 CA0genhJZxekiCz249qnXxch0AFJR8E9FLiahq8RO7Y6KrYOVs6hyOw9dFYt91ZD beMUnegxsaH3+bDl7vrYLX2TA/eFiQpjNbgAwUbwOqkusOru/SPoOLO1ISbnp/wL J/L0Q== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 45kbmy9d6d-13 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Wed, 26 Mar 2025 16:48:59 +0000 (GMT) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.0.133) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Wed, 26 Mar 2025 16:48:49 +0000 From: Matt Coster Date: Wed, 26 Mar 2025 16:48:32 +0000 Subject: [PATCH v5 12/18] drm/imagination: Use callbacks for fw irq handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250326-sets-bxs-4-64-patch-v1-v5-12-e4c46e8280a9@imgtec.com> References: <20250326-sets-bxs-4-64-patch-v1-v5-0-e4c46e8280a9@imgtec.com> In-Reply-To: <20250326-sets-bxs-4-64-patch-v1-v5-0-e4c46e8280a9@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Michal Wilczynski" , Alessio Belle , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7264; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=AGBvIBv7eUE58QmH1vxKVNMYOVNCjNhYNw59cwAmh/o=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaQ/0X/6dNXOj5uz5JqW//wulnuh/MfNnbdU+99MSXins nuy4/Ii6Y5SFgYxDgZZMUWWHSssV6j9UdOSuPGrGGYOKxPIEAYuTgGYCIsDwy/mTvG8mq3fWRkM N+/m+fNyl47zL4NfJz6z/AoTcjJgVS9iZOhq2NW47YLr1uv2XuZxL98f87OxCjaqFtB9vTEq4p2 aJT8A X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: Wg3OsmSnEgPpzeCYAIwQcTIYwUhxhmAk X-Authority-Analysis: v=2.4 cv=L+sdQ/T8 c=1 sm=1 tr=0 ts=67e42ffb cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=ETbM1kImDFEA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=Y33Pwm5EY2qbWUOeHhAA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: Wg3OsmSnEgPpzeCYAIwQcTIYwUhxhmAk This allows for more versatility in checking and clearing firmware registers used for interrupt handling. Signed-off-by: Matt Coster --- Changes in v5: - None - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-= 12-d987cf4ca439@imgtec.com Changes in v4: - None - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-= 12-143b3dbef02f@imgtec.com Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-= 14-3fd45d9fb0cf@imgtec.com Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 14-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.h | 18 +++++++++++++ drivers/gpu/drm/imagination/pvr_fw.h | 45 +++++++++------------------= ---- drivers/gpu/drm/imagination/pvr_fw_meta.c | 22 ++++++++++----- drivers/gpu/drm/imagination/pvr_fw_mips.c | 22 ++++++++++----- 4 files changed, 63 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 12bf0b9e5bfb48ef9e5ed9faa44e0896b7555f49..eb5da8c7040fc9e9751f433279c= b0c92fd4d1336 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -739,4 +739,22 @@ pvr_ioctl_union_padding_check(void *instance, size_t u= nion_offset, __union_size, __member_size); \ }) =20 +/* + * These utility functions should more properly be placed in pvr_fw.h, but= that + * would cause a dependency cycle between that header and this one. Since + * they're primarily used in pvr_device.c, let's put them in here for now. + */ + +static __always_inline bool +pvr_fw_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_dev->fw_dev.defs->irq_pending(pvr_dev); +} + +static __always_inline void +pvr_fw_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_dev->fw_dev.defs->irq_clear(pvr_dev); +} + #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 88ad713468ce3a1ee459b04dde5363c24791a4f1..ab69f40a7fbc6304171f16dd16d= 825a68b0362a5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -167,29 +167,22 @@ struct pvr_fw_defs { int (*wrapper_init)(struct pvr_device *pvr_dev); =20 /** - * @irq: FW Interrupt information. + * @irq_pending: Check interrupt status register for pending interrupts. * - * Those are processor dependent, and should be initialized by the - * processor backend in pvr_fw_funcs::init(). + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. */ - struct { - /** @status_reg: FW interrupt status register. */ - u32 status_reg; + bool (*irq_pending)(struct pvr_device *pvr_dev); =20 - /** - * @clear_reg: FW interrupt clear register. - * - * If @status_reg =3D=3D @clear_reg, we clear by write a bit to zero, - * otherwise we clear by writing a bit to one. - */ - u32 clear_reg; - - /** @status_mask: Bitmask of events to listen for in the status_reg. */ - u32 status_mask; - - /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ - u32 clear_mask; - } irq; + /** + * @irq_clear: Clear pending interrupts. + * + * @pvr_dev: Target PowerVR device. + * + * This function is mandatory. + */ + void (*irq_clear)(struct pvr_device *pvr_dev); =20 /** * @has_fixed_data_addr: Specify whether the firmware fixed data must be = loaded at the @@ -390,18 +383,6 @@ struct pvr_fw_device { } fw_objs; }; =20 -#define pvr_fw_irq_read_reg(pvr_dev, name) \ - pvr_cr_read32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg) - -#define pvr_fw_irq_write_reg(pvr_dev, name, value) \ - pvr_cr_write32((pvr_dev), (pvr_dev)->fw_dev.defs->irq.name ## _reg, value) - -#define pvr_fw_irq_pending(pvr_dev) \ - (pvr_fw_irq_read_reg(pvr_dev, status) & (pvr_dev)->fw_dev.defs->irq.statu= s_mask) - -#define pvr_fw_irq_clear(pvr_dev) \ - pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) - enum pvr_fw_processor_type { PVR_FW_PROCESSOR_TYPE_META =3D 0, PVR_FW_PROCESSOR_TYPE_MIPS, diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index 62ddfea6b7306784b979ce209bfdf4a9938f8984..d72e0eae9e4b16cb31c48797ffc= f5138d2728862 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -533,6 +533,20 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct p= vr_fw_object *fw_obj) fw_obj->fw_mm_node.start, fw_obj->fw_mm_node.size); } =20 +static bool +pvr_meta_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS) & + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN; +} + +static void +pvr_meta_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS, + ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK); +} + const struct pvr_fw_defs pvr_fw_defs_meta =3D { .init =3D pvr_meta_init, .fw_process =3D pvr_meta_fw_process, @@ -540,11 +554,7 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .vm_unmap =3D pvr_meta_vm_unmap, .get_fw_addr_with_offset =3D pvr_meta_get_fw_addr_with_offset, .wrapper_init =3D pvr_meta_wrapper_init, - .irq =3D { - .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, - .status_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, - .clear_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, - }, + .irq_pending =3D pvr_meta_irq_pending, + .irq_clear =3D pvr_meta_irq_clear, .has_fixed_data_addr =3D false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index 2c3172841886b70eb7a9992ec3851f18adcad8d5..524a9bd0a20b64c509f5708cc61= d93b4c864b835 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -227,6 +227,20 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object = *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } =20 +static bool +pvr_mips_irq_pending(struct pvr_device *pvr_dev) +{ + return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) & + ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN; +} + +static void +pvr_mips_irq_clear(struct pvr_device *pvr_dev) +{ + pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, + ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN); +} + const struct pvr_fw_defs pvr_fw_defs_mips =3D { .init =3D pvr_mips_init, .fini =3D pvr_mips_fini, @@ -235,11 +249,7 @@ const struct pvr_fw_defs pvr_fw_defs_mips =3D { .vm_unmap =3D pvr_vm_mips_unmap, .get_fw_addr_with_offset =3D pvr_mips_get_fw_addr_with_offset, .wrapper_init =3D pvr_mips_wrapper_init, - .irq =3D { - .status_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, - .clear_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, - .status_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, - .clear_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, - }, + .irq_pending =3D pvr_mips_irq_pending, + .irq_clear =3D pvr_mips_irq_clear, .has_fixed_data_addr =3D true, }; --=20 2.49.0