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Tue, 25 Mar 2025 07:43:00 -0700 (PDT) From: Xu Lu To: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, alex@ghiti.fr Cc: lihangjing@bytedance.com, xieyongji@bytedance.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, Xu Lu Subject: [PATCH] iommu: riscv: Split 8-byte accesses on 32 bit I/O bus platform Date: Tue, 25 Mar 2025 22:42:52 +0800 Message-Id: <20250325144252.27403-1-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a new configuration CONFIG_RISCV_IOMMU_32BIT to enable splitting 8-byte access into 4-byte transactions for hardware platform whose I/O bus limits access to 4-byte transfers. Signed-off-by: Xu Lu --- drivers/iommu/riscv/Kconfig | 9 +++++++++ drivers/iommu/riscv/iommu.h | 28 +++++++++++++++++++++++----- 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/riscv/Kconfig b/drivers/iommu/riscv/Kconfig index c071816f59a6..b7c9ea22d969 100644 --- a/drivers/iommu/riscv/Kconfig +++ b/drivers/iommu/riscv/Kconfig @@ -18,3 +18,12 @@ config RISCV_IOMMU_PCI def_bool y if RISCV_IOMMU && PCI_MSI help Support for the PCIe implementation of RISC-V IOMMU architecture. + +config RISCV_IOMMU_32BIT + bool "Support 4-Byte Accesses on RISC-V IOMMU Registers" + depends on RISCV_IOMMU + default n + help + Support hardware platform whose I/O bus limits access to 4-byte + transfers. When enabled, all accesses to IOMMU registers will be + split into 4-byte accesses. diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd5495..0e3552a8142d 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -14,6 +14,10 @@ #include #include #include +#ifdef CONFIG_RISCV_IOMMU_32BIT +#include +#include +#endif =20 #include "iommu-bits.h" =20 @@ -69,21 +73,35 @@ void riscv_iommu_disable(struct riscv_iommu_device *iom= mu); #define riscv_iommu_readl(iommu, addr) \ readl_relaxed((iommu)->reg + (addr)) =20 -#define riscv_iommu_readq(iommu, addr) \ - readq_relaxed((iommu)->reg + (addr)) - #define riscv_iommu_writel(iommu, addr, val) \ writel_relaxed((val), (iommu)->reg + (addr)) =20 +#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeou= t_us) \ + readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ + delay_us, timeout_us) + +#ifndef CONFIG_RISCV_IOMMU_32BIT +#define riscv_iommu_readq(iommu, addr) \ + readq_relaxed((iommu)->reg + (addr)) + #define riscv_iommu_writeq(iommu, addr, val) \ writeq_relaxed((val), (iommu)->reg + (addr)) =20 #define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeou= t_us) \ readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \ delay_us, timeout_us) +#else /* CONFIG_RISCV_IOMMU_32BIT */ +#define riscv_iommu_readq(iommu, addr) \ + hi_lo_readq_relaxed((iommu)->reg + (addr)) =20 -#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeou= t_us) \ - readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ +#define riscv_iommu_writeq(iommu, addr, val) \ + ((addr =3D=3D RISCV_IOMMU_REG_IOHPMCYCLES) ? \ + lo_hi_writeq_relaxed((val), (iommu)->reg + (addr)) : \ + hi_lo_writeq_relaxed((val), (iommu)->reg + (addr))) + +#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeou= t_us) \ + readx_poll_timeout(hi_lo_readq_relaxed, (iommu)->reg + (addr), val, cond,= \ delay_us, timeout_us) +#endif /* CONFIG_RISCV_IOMMU_32BIT */ =20 #endif --=20 2.20.1