From nobody Mon Feb 9 22:02:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9F721FBE8C; Tue, 25 Mar 2025 18:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742928597; cv=none; b=VvXJScxh4ZH4Om2QAz1v4LEJVB6xLoimaaLB3fgWdpVMRaGj+Eu0UuBY280AAynrGhTiLbkDAEqTqUQUh8PIB04xH/9YDMM11wD4E18GI4ki2uTsAhRbqSAjgEyLtqx+unVMNuejfeG1dS4FwEp2ecVT2DCV///OBRlgGYrwoh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742928597; c=relaxed/simple; bh=MTEosjvyIXeiLdAt6pHE/37ogwWlAb8fkZ9xuDBjlXU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cIJ6ycujrwTH8tTNPn097sgMPMp1FsM6JojmJW6wrknKpVoMKezq7AEd0ZGVed3jXzkS5xItF+ieG6DJIUNeYwl+77a0RiwsSXSJv5dx7e+j5RNnbMCnBCm/HB7d2zMb43L+lUNBH1Z2W2WJya0Aj+iNI6yeuckN2b+8/d+tZvI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rD1ZwRSq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rD1ZwRSq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 13CE1C4CEF0; Tue, 25 Mar 2025 18:49:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742928597; bh=MTEosjvyIXeiLdAt6pHE/37ogwWlAb8fkZ9xuDBjlXU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=rD1ZwRSqnL4gATGlNbimvyckDdYZVTmRiUz4W3WrKSxahaGYSWZtNWhBcMoviXiQs eRK0vEpMAinAoAcNtzqxf8p1sEWzPxmATrJl5J5KMt2HlwLWnG1jJHvfYsHS+Z2fDF JqNF8jbxT7N2FjLDBhCVkxgUMfFCtbFnIfBbZYtvXKmjWOt7u6vXRJJI5gIsP/CHym bcJmM+aWDvVYwv85synre1qZD8mcKXKtbJw9zQA9YxhBm5PDJsyrtUZnccg/v9BhcV iQMbZtSWRqJKml4nfj070UT1LTuLlDKCotBeT98rm5NAEQuxr7PRqxKzqCcR+WwLpt jU1IUdDhuwVzw== From: Mark Brown Date: Tue, 25 Mar 2025 18:48:25 +0000 Subject: [PATCH 6.1 11/12] KVM: arm64: Calculate cptr_el2 traps on activating traps Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250325-stable-sve-6-1-v1-11-83259d427d84@kernel.org> References: <20250325-stable-sve-6-1-v1-0-83259d427d84@kernel.org> In-Reply-To: <20250325-stable-sve-6-1-v1-0-83259d427d84@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , James Morse , Suzuki K Poulose , Oliver Upton , Oleg Nesterov Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvmarm@lists.cs.columbia.edu, Mark Brown , Fuad Tabba , James Clark X-Mailer: b4 0.15-dev-1b0d6 X-Developer-Signature: v=1; a=openpgp-sha256; l=5744; i=broonie@kernel.org; h=from:subject:message-id; bh=EPws4FYo338+tDiFF/F0cYfIo4BhRk8Cba6FR1NjCVM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBn4vqui/gvKGQDYx3L/to0dgD9sTP5F1b8ef2TZv5e aQopOeSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ+L6rgAKCRAk1otyXVSH0A/uB/ 9/8H9xKi3OU1Y6QF68vUsI3pqvlXEymJKeBGUSu4+mpG9PWoCHNrvUljq4/hUm6xDh4X2yLbiQo4Qd aN0XfI3/iRNq5MnFOWVQki+757Ub7g5P55v4gj4f4SOlMq5ackGuySBFfabYtDXQgKbyQ4KU75LhdJ GLf4E2AfPOa2zVJ7GpB+rYgcFso2Ci5QJnMzJA6Iix//UL7Y9V3PAVYeWlucCHYQ+8Mi8V0SkHNWjU n/POr85nHtrdegR7IFmnepuaeqSHdMfyqGzK7b8hdBKiyrqQFviFF9P8IeCgXcpG5EqcC1iQh5D687 qTckrPOG+4DhTuNdZ/LmkKuZfmepYG X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB From: Fuad Tabba [ Upstream commit 2fd5b4b0e7b440602455b79977bfa64dea101e6c ] Similar to VHE, calculate the value of cptr_el2 from scratch on activate traps. This removes the need to store cptr_el2 in every vcpu structure. Moreover, some traps, such as whether the guest owns the fp registers, need to be set on every vcpu run. Reported-by: James Clark Fixes: 5294afdbf45a ("KVM: arm64: Exclude FP ownership from kvm_vcpu_arch") Signed-off-by: Fuad Tabba Link: https://lore.kernel.org/r/20241216105057.579031-13-tabba@google.com Signed-off-by: Marc Zyngier Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 1 - arch/arm64/kvm/arm.c | 1 - arch/arm64/kvm/hyp/nvhe/pkvm.c | 15 --------------- arch/arm64/kvm/hyp/nvhe/switch.c | 38 +++++++++++++++++++++++++++--------= --- 4 files changed, 27 insertions(+), 28 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 757f4dea1e563657eb5c79e624e4b91f514a113a..c13a0d5907e8756cbbf45884740= 3bab78de7947c 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -330,7 +330,6 @@ struct kvm_vcpu_arch { /* Values of trap registers for the guest. */ u64 hcr_el2; u64 mdcr_el2; - u64 cptr_el2; =20 /* Values of trap registers for the host before guest entry. */ u64 mdcr_el2_host; diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 3a05f364b4b6d4a47148e8bd83e7bcf92a1ccbea..4629505d5fa80e8151eebb4eed5= 00d46258e63f6 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1230,7 +1230,6 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_v= cpu *vcpu, } =20 vcpu_reset_hcr(vcpu); - vcpu->arch.cptr_el2 =3D CPTR_EL2_DEFAULT; =20 /* * Handle the "start in power-off" case. diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 85d3b7ae720fb0ae78e79709e9c555ab01531e0d..93586bf80ec9f2bab44625253fe= d71654e22c87c 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -17,7 +17,6 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu) const u64 feature_ids =3D pvm_read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1); u64 hcr_set =3D HCR_RW; u64 hcr_clear =3D 0; - u64 cptr_set =3D 0; =20 /* Protected KVM does not support AArch32 guests. */ BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), @@ -44,16 +43,10 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vc= pu) /* Trap AMU */ if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) { hcr_clear |=3D HCR_AMVOFFEN; - cptr_set |=3D CPTR_EL2_TAM; } =20 - /* Trap SVE */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) - cptr_set |=3D CPTR_EL2_TZ; - vcpu->arch.hcr_el2 |=3D hcr_set; vcpu->arch.hcr_el2 &=3D ~hcr_clear; - vcpu->arch.cptr_el2 |=3D cptr_set; } =20 /* @@ -83,7 +76,6 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu) const u64 feature_ids =3D pvm_read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1); u64 mdcr_set =3D 0; u64 mdcr_clear =3D 0; - u64 cptr_set =3D 0; =20 /* Trap/constrain PMU */ if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), feature_ids)) { @@ -110,13 +102,8 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *v= cpu) if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids= )) mdcr_set |=3D MDCR_EL2_TTRF; =20 - /* Trap Trace */ - if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids)) - cptr_set |=3D CPTR_EL2_TTA; - vcpu->arch.mdcr_el2 |=3D mdcr_set; vcpu->arch.mdcr_el2 &=3D ~mdcr_clear; - vcpu->arch.cptr_el2 |=3D cptr_set; } =20 /* @@ -167,8 +154,6 @@ static void pvm_init_trap_regs(struct kvm_vcpu *vcpu) /* Clear res0 and set res1 bits to trap potential new features. */ vcpu->arch.hcr_el2 &=3D ~(HCR_RES0); vcpu->arch.mdcr_el2 &=3D ~(MDCR_EL2_RES0); - vcpu->arch.cptr_el2 |=3D CPTR_NVHE_EL2_RES1; - vcpu->arch.cptr_el2 &=3D ~(CPTR_NVHE_EL2_RES0); } =20 /* diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/swi= tch.c index 844c466f1b1f26620582972038ac2bd81f876182..58171926f9ba23844997ff02406= 518a312eb8bb7 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -36,23 +36,39 @@ DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); =20 extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc); =20 -static void __activate_traps(struct kvm_vcpu *vcpu) +static void __activate_cptr_traps(struct kvm_vcpu *vcpu) { - u64 val; + u64 val =3D CPTR_EL2_TAM; /* Same bit irrespective of E2H */ =20 - ___activate_traps(vcpu); - __activate_traps_common(vcpu); + /* !hVHE case upstream */ + if (1) { + val |=3D CPTR_EL2_TTA | CPTR_NVHE_EL2_RES1; =20 - val =3D vcpu->arch.cptr_el2; - val |=3D CPTR_EL2_TTA | CPTR_EL2_TAM; - if (!guest_owns_fp_regs(vcpu)) { - val |=3D CPTR_EL2_TFP | CPTR_EL2_TZ; - __activate_traps_fpsimd32(vcpu); - } - if (cpus_have_final_cap(ARM64_SME)) + /* + * Always trap SME since it's not supported in KVM. + * TSM is RES1 if SME isn't implemented. + */ val |=3D CPTR_EL2_TSM; =20 + if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs(vcpu)) + val |=3D CPTR_EL2_TZ; + + if (!guest_owns_fp_regs(vcpu)) + val |=3D CPTR_EL2_TFP; + } + + if (!guest_owns_fp_regs(vcpu)) + __activate_traps_fpsimd32(vcpu); + write_sysreg(val, cptr_el2); +} + +static void __activate_traps(struct kvm_vcpu *vcpu) +{ + ___activate_traps(vcpu); + __activate_traps_common(vcpu); + __activate_cptr_traps(vcpu); + write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); =20 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { --=20 2.39.5