From nobody Fri Dec 19 19:17:58 2025 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49CC426989A for ; Mon, 24 Mar 2025 17:33:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742837615; cv=none; b=a1FiEJ1akB30RIkPY8KwBvrbT1GR+76lv9qygXBIeWQRv3kXBWPMfQS3JG8h7P2gNHjQIsYvh0zfwHuoTPbif84OJg0m4S0ichOYdcS63IQFybrbNMornXjUjPlP/r3Zap9HryrHM3dFFwQdsrT8dQIxs0qY45GFuOakmBmBof8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742837615; c=relaxed/simple; bh=FoH7tcwE2GeOWEZefq9DrN/eLcHxhIICNsQu5pyoq5E=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=lTzrZX2li4UWkgSQO+g132CaBYSRIOefA5v0FIjnAIUNhTSK0ynxY+prr+VbHlOYSlTpLDtJt8J+cP3+z+J1/DwXFgbXz+dAI7XBdBqOwsYI8Z2XaL2bKGeAhpT9NK7lXoT5ehyQyc5Zn842vLRy+ZzcEYkEGRFToHN19BhV55A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=zcbco0U3; arc=none smtp.client-ip=209.85.214.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--mizhang.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="zcbco0U3" Received: by mail-pl1-f202.google.com with SMTP id d9443c01a7336-22647ff3cf5so65613235ad.0 for ; Mon, 24 Mar 2025 10:33:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1742837612; x=1743442412; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=4OJAB7txnhcLTcXVYrfnb5vnccIxSZ8DO2qJNaOYpK0=; b=zcbco0U3TX5qrbjFdtCpf+5jZIbdBVS0xbLIab9r9HToLxKrkgCxe0oTA0nEUXujd+ Ft6k7K4iQbVnW865TAQbBDFhcqgwEaXY2uPlwvegZBqOaMMNML1Gb17Luxb3EK7iTUeN 8jA5sqykKHzcPL+YApgKBQIu8O+tN0Atm/RetygYqD/JbeoQMsdQ89fNkhfNUAQSlgYS LqRg9s4JGH8vQKX1WKUHfKqFaL2iLTyebEqkpey8y4Xz0YHxts1WkxMpFZ3P3x3+/N1H qLnHECavEVOOPp8gq12fo2b8xQsf/G2Cb5sMoVLZYsNdbx50c4fDfyW3AAmAY5VySzeE Y6AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742837612; x=1743442412; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4OJAB7txnhcLTcXVYrfnb5vnccIxSZ8DO2qJNaOYpK0=; b=uY/pxaqINL2pxGKpFxWOTg2iKFNGrqI/PVCLz8yUklm5l5X/SGKrYCEauQeuduLR8L L+yUYQzBPCftHtXi1PMBS2lmP751HXaBqDXh1OZeOh4nuxlDJFOwnYMcTotf/hkrxvi3 TXVTv5u5A0gPxa30fRKoNGVQ8uWI26VpfbeCYafIj7j/8i72S7kRR1gAdrTeaPpcnOtT AohAQJxdErTu6Lt7idf3hbGiVPg+iGgAEWnnXkpFu2iPEBIoyl7rhoTuizp6cihqs+PT rxE8oMHXaHqrf9Z28KuyXFngAnFkwKEQJQk+zNwy3P/M7X3E44TxVYmrc7l+BkqspXfM Ne8w== X-Forwarded-Encrypted: i=1; AJvYcCXfBXVPRI5pj59L4mcLi+bR5p1aE4VHNSlklPfTjunnptRSYf0k2ZbsSGDfp0hmerLgcgsKs/tbhzvjSuI=@vger.kernel.org X-Gm-Message-State: AOJu0YxWT93aFGEbUljx7ADs6Lm7BMGfj8w0r9Xl4iZsK72awg8qENYR ZSaPx9xdtHufQPAmEnCJLEpASlSFT1g9gE7JSruZvqY+TeFke87mmKo7We4Q4d4V3Q6dUtV/4S9 Q1VTU4g== X-Google-Smtp-Source: AGHT+IEWTl/R0f1qfRJlE3emUEFa0yj+sOW5pbNSYV28FCQ8VzTuf09ewlLJoB3GkYH0qtajqpf5IDFU59K+ X-Received: from plbkw5.prod.google.com ([2002:a17:902:f905:b0:226:342c:5750]) (user=mizhang job=prod-delivery.src-stubby-dispatcher) by 2002:a17:903:985:b0:220:c813:dfce with SMTP id d9443c01a7336-22780e0a965mr250833335ad.39.1742837612577; Mon, 24 Mar 2025 10:33:32 -0700 (PDT) Reply-To: Mingwei Zhang Date: Mon, 24 Mar 2025 17:31:05 +0000 In-Reply-To: <20250324173121.1275209-1-mizhang@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250324173121.1275209-1-mizhang@google.com> X-Mailer: git-send-email 2.49.0.395.g12beb8f557-goog Message-ID: <20250324173121.1275209-26-mizhang@google.com> Subject: [PATCH v4 25/38] KVM: x86/pmu: Add AMD PMU registers to direct access list From: Mingwei Zhang To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Sean Christopherson , Paolo Bonzini Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Liang@google.com, Kan , "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, Mingwei Zhang , Yongwei Ma , Xiong Zhang , Dapeng Mi , Jim Mattson , Sandipan Das , Zide Chen , Eranian Stephane , Das Sandipan , Shukla Manali , Nikunj Dadhania Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sandipan Das Add all PMU-related MSRs (including legacy K7 MSRs) to the list of possible direct access MSRs. Most of them will not be intercepted when using passthrough PMU. Signed-off-by: Sandipan Das Signed-off-by: Mingwei Zhang --- arch/x86/kvm/svm/svm.c | 24 ++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index a713c803a3a3..bff351992468 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -143,6 +143,30 @@ static const struct svm_direct_access_msrs { { .index =3D X2APIC_MSR(APIC_TMICT), .always =3D false }, { .index =3D X2APIC_MSR(APIC_TMCCT), .always =3D false }, { .index =3D X2APIC_MSR(APIC_TDCR), .always =3D false }, + { .index =3D MSR_K7_EVNTSEL0, .always =3D false }, + { .index =3D MSR_K7_PERFCTR0, .always =3D false }, + { .index =3D MSR_K7_EVNTSEL1, .always =3D false }, + { .index =3D MSR_K7_PERFCTR1, .always =3D false }, + { .index =3D MSR_K7_EVNTSEL2, .always =3D false }, + { .index =3D MSR_K7_PERFCTR2, .always =3D false }, + { .index =3D MSR_K7_EVNTSEL3, .always =3D false }, + { .index =3D MSR_K7_PERFCTR3, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTL0, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTR0, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTL1, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTR1, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTL2, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTR2, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTL3, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTR3, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTL4, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTR4, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTL5, .always =3D false }, + { .index =3D MSR_F15H_PERF_CTR5, .always =3D false }, + { .index =3D MSR_AMD64_PERF_CNTR_GLOBAL_CTL, .always =3D false }, + { .index =3D MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, .always =3D false }, + { .index =3D MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, .always =3D false }, + { .index =3D MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, .always =3D false }, { .index =3D MSR_INVALID, .always =3D false }, }; =20 diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 9d7cdb8fbf87..ae71bf5f12d0 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -44,7 +44,7 @@ static inline struct page *__sme_pa_to_page(unsigned long= pa) #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 =20 -#define MAX_DIRECT_ACCESS_MSRS 48 +#define MAX_DIRECT_ACCESS_MSRS 72 #define MSRPM_OFFSETS 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; --=20 2.49.0.395.g12beb8f557-goog