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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v3 16/20] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0 Date: Mon, 24 Mar 2025 15:20:37 +0100 Message-ID: <20250324142042.29010-17-darwi@linutronix.de> In-Reply-To: <20250324142042.29010-1-darwi@linutronix.de> References: <20250324142042.29010-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file to version v2.0, as generated by x86-cpuid-db. Summary of the v2.0 changes: * Introduce the leaves: - Leaf 0x00000003, Transmeta Processor serial number - Leaf 0x80860000, Transmeta max leaf number + CPU vendor ID - Leaf 0x80860001, Transmeta extended CPU information - Leaf 0x80860002, Transmeta Code Morphing Software (CMS) enumeration - Leaf 0x80860003 =3D> 0x80860006, Transmeta CPU information string - Leaf 0x80860007, Transmeta "live" CPU information - Leaf 0xc0000000, Centaur/Zhaoxin's max leaf number - Leaf 0xc0000001, Centaur/Zhaoxin's extended CPU features * Add a 0x prefix for leaves 0x0 to 0x9. This maintains consistency with the rest of the CSV entries. * Add the new bitfields: - Leaf 0x7: nmi_src, NMI-source reporting - Leaf 0x80000001: e_base_type and e_mmx (Transmeta) * Update the section headers for leaves 0x80000000 and 0x80000005 to indicate that they are also valid for Transmeta. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.0/CHANGELOG.r= st --- Notes: Leaf 0x3, being not unique to Transmeta, is handled at the generated CSV file v2.3 update, later in this patch queue. =20 Leaf 0x80000001 EDX:23 bit, e_mmx, is also available on AMD. A bugfix is already merged at x86-cpuid-db's -tip for that, and it will be part of the project's upcoming v2.4 release.: =20 https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/commit/65fff25daa41 tools/arch/x86/kcpuid/cpuid.csv | 648 +++++++++++++++++++------------- 1 file changed, 382 insertions(+), 266 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index d751eb8585d0..d0f7159f99ba 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v1.0 +# Generator: x86-cpuid-db v2.0 =20 # # Auto-generated file. @@ -12,297 +12,306 @@ # Leaf 0H # Maximum standard leaf number + CPU vendor string =20 - 0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported - 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 - 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 - 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + 0x0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 + 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 + 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 =20 # Leaf 1H # CPU FMS (Family/Model/Stepping) + standard feature flags =20 - 1, 0, eax, 3:0, stepping , Stepping= ID - 1, 0, eax, 7:4, base_model , Base CPU= model ID - 1, 0, eax, 11:8, base_family_id , Base CPU= family ID - 1, 0, eax, 13:12, cpu_type , CPU type - 1, 0, eax, 19:16, ext_model , Extended= CPU model ID - 1, 0, eax, 27:20, ext_family , Extended= CPU family ID - 1, 0, ebx, 7:0, brand_id , Brand in= dex - 1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size - 1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count - 1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID - 1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) - 1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support - 1, 0, ecx, 2, dtes64 , 64-bit D= S save area - 1, 0, ecx, 3, monitor , MONITOR/= MWAIT support - 1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store - 1, 0, ecx, 5, vmx , Virtual = Machine Extensions - 1, 0, ecx, 6, smx , Safer Mo= de Extensions - 1, 0, ecx, 7, est , Enhanced= Intel SpeedStep - 1, 0, ecx, 8, tm2 , Thermal = Monitor 2 - 1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 - 1, 0, ecx, 10, cid , L1 Conte= xt ID - 1, 0, ecx, 11, sdbg , Sillicon= Debug - 1, 0, ecx, 12, fma , FMA exte= nsions using YMM state - 1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support - 1, 0, ecx, 14, xtpr , xTPR Upd= ate Control - 1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability - 1, 0, ecx, 17, pcid , Process-= context identifiers - 1, 0, ecx, 18, dca , Direct C= ache Access - 1, 0, ecx, 19, sse4_1 , SSE4.1 - 1, 0, ecx, 20, sse4_2 , SSE4.2 - 1, 0, ecx, 21, x2apic , X2APIC s= upport - 1, 0, ecx, 22, movbe , MOVBE in= struction support - 1, 0, ecx, 23, popcnt , POPCNT i= nstruction support - 1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation - 1, 0, ecx, 25, aes , AES inst= ructions - 1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support - 1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS - 1, 0, ecx, 28, avx , AVX inst= ructions support - 1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support - 1, 0, ecx, 30, rdrand , RDRAND i= nstruction support - 1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system - 1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) - 1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions - 1, 0, edx, 2, de , Debuggin= g Extensions - 1, 0, edx, 3, pse , Page Siz= e Extension - 1, 0, edx, 4, tsc , Time Sta= mp Counter - 1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) - 1, 0, edx, 6, pae , Physical= Address Extensions - 1, 0, edx, 7, mce , Machine = Check Exception - 1, 0, edx, 8, cx8 , CMPXCHG8= B instruction - 1, 0, edx, 9, apic , APIC on-= chip - 1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs - 1, 0, edx, 12, mtrr , Memory T= ype Range Registers - 1, 0, edx, 13, pge , Page Glo= bal Extensions - 1, 0, edx, 14, mca , Machine = Check Architecture - 1, 0, edx, 15, cmov , Conditio= nal Move Instruction - 1, 0, edx, 16, pat , Page Att= ribute Table - 1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) - 1, 0, edx, 18, pn , Processo= r Serial Number - 1, 0, edx, 19, clflush , CLFLUSH = instruction - 1, 0, edx, 21, dts , Debug St= ore - 1, 0, edx, 22, acpi , Thermal = monitor and clock control - 1, 0, edx, 23, mmx , MMX inst= ructions - 1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions - 1, 0, edx, 25, sse , SSE inst= ructions - 1, 0, edx, 26, sse2 , SSE2 ins= tructions - 1, 0, edx, 27, ss , Self Sno= op - 1, 0, edx, 28, ht , Hyper-th= reading - 1, 0, edx, 29, tm , Thermal = Monitor - 1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved - 1, 0, edx, 31, pbe , Pending = Break Enable + 0x1, 0, eax, 3:0, stepping , Stepping= ID + 0x1, 0, eax, 7:4, base_model , Base CPU= model ID + 0x1, 0, eax, 11:8, base_family_id , Base CPU= family ID + 0x1, 0, eax, 13:12, cpu_type , CPU type + 0x1, 0, eax, 19:16, ext_model , Extended= CPU model ID + 0x1, 0, eax, 27:20, ext_family , Extended= CPU family ID + 0x1, 0, ebx, 7:0, brand_id , Brand in= dex + 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size + 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 0x1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID + 0x1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) + 0x1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support + 0x1, 0, ecx, 2, dtes64 , 64-bit D= S save area + 0x1, 0, ecx, 3, monitor , MONITOR/= MWAIT support + 0x1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store + 0x1, 0, ecx, 5, vmx , Virtual = Machine Extensions + 0x1, 0, ecx, 6, smx , Safer Mo= de Extensions + 0x1, 0, ecx, 7, est , Enhanced= Intel SpeedStep + 0x1, 0, ecx, 8, tm2 , Thermal = Monitor 2 + 0x1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 + 0x1, 0, ecx, 10, cid , L1 Conte= xt ID + 0x1, 0, ecx, 11, sdbg , Sillicon= Debug + 0x1, 0, ecx, 12, fma , FMA exte= nsions using YMM state + 0x1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support + 0x1, 0, ecx, 14, xtpr , xTPR Upd= ate Control + 0x1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability + 0x1, 0, ecx, 17, pcid , Process-= context identifiers + 0x1, 0, ecx, 18, dca , Direct C= ache Access + 0x1, 0, ecx, 19, sse4_1 , SSE4.1 + 0x1, 0, ecx, 20, sse4_2 , SSE4.2 + 0x1, 0, ecx, 21, x2apic , X2APIC s= upport + 0x1, 0, ecx, 22, movbe , MOVBE in= struction support + 0x1, 0, ecx, 23, popcnt , POPCNT i= nstruction support + 0x1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation + 0x1, 0, ecx, 25, aes , AES inst= ructions + 0x1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support + 0x1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS + 0x1, 0, ecx, 28, avx , AVX inst= ructions support + 0x1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support + 0x1, 0, ecx, 30, rdrand , RDRAND i= nstruction support + 0x1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system + 0x1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) + 0x1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions + 0x1, 0, edx, 2, de , Debuggin= g Extensions + 0x1, 0, edx, 3, pse , Page Siz= e Extension + 0x1, 0, edx, 4, tsc , Time Sta= mp Counter + 0x1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) + 0x1, 0, edx, 6, pae , Physical= Address Extensions + 0x1, 0, edx, 7, mce , Machine = Check Exception + 0x1, 0, edx, 8, cx8 , CMPXCHG8= B instruction + 0x1, 0, edx, 9, apic , APIC on-= chip + 0x1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs + 0x1, 0, edx, 12, mtrr , Memory T= ype Range Registers + 0x1, 0, edx, 13, pge , Page Glo= bal Extensions + 0x1, 0, edx, 14, mca , Machine = Check Architecture + 0x1, 0, edx, 15, cmov , Conditio= nal Move Instruction + 0x1, 0, edx, 16, pat , Page Att= ribute Table + 0x1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) + 0x1, 0, edx, 18, pn , Processo= r Serial Number + 0x1, 0, edx, 19, clflush , CLFLUSH = instruction + 0x1, 0, edx, 21, dts , Debug St= ore + 0x1, 0, edx, 22, acpi , Thermal = monitor and clock control + 0x1, 0, edx, 23, mmx , MMX inst= ructions + 0x1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions + 0x1, 0, edx, 25, sse , SSE inst= ructions + 0x1, 0, edx, 26, sse2 , SSE2 ins= tructions + 0x1, 0, edx, 27, ss , Self Sno= op + 0x1, 0, edx, 28, ht , Hyper-th= reading + 0x1, 0, edx, 29, tm , Thermal = Monitor + 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 0x1, 0, edx, 31, pbe , Pending = Break Enable =20 # Leaf 2H # Intel cache and TLB information one-byte descriptors =20 - 2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried - 2, 0, eax, 15:8, desc1 , Descript= or #1 - 2, 0, eax, 23:16, desc2 , Descript= or #2 - 2, 0, eax, 30:24, desc3 , Descript= or #3 - 2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set - 2, 0, ebx, 7:0, desc4 , Descript= or #4 - 2, 0, ebx, 15:8, desc5 , Descript= or #5 - 2, 0, ebx, 23:16, desc6 , Descript= or #6 - 2, 0, ebx, 30:24, desc7 , Descript= or #7 - 2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set - 2, 0, ecx, 7:0, desc8 , Descript= or #8 - 2, 0, ecx, 15:8, desc9 , Descript= or #9 - 2, 0, ecx, 23:16, desc10 , Descript= or #10 - 2, 0, ecx, 30:24, desc11 , Descript= or #11 - 2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set - 2, 0, edx, 7:0, desc12 , Descript= or #12 - 2, 0, edx, 15:8, desc13 , Descript= or #13 - 2, 0, edx, 23:16, desc14 , Descript= or #14 - 2, 0, edx, 30:24, desc15 , Descript= or #15 - 2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + 0x2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 0x2, 0, eax, 15:8, desc1 , Descript= or #1 + 0x2, 0, eax, 23:16, desc2 , Descript= or #2 + 0x2, 0, eax, 30:24, desc3 , Descript= or #3 + 0x2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set + 0x2, 0, ebx, 7:0, desc4 , Descript= or #4 + 0x2, 0, ebx, 15:8, desc5 , Descript= or #5 + 0x2, 0, ebx, 23:16, desc6 , Descript= or #6 + 0x2, 0, ebx, 30:24, desc7 , Descript= or #7 + 0x2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set + 0x2, 0, ecx, 7:0, desc8 , Descript= or #8 + 0x2, 0, ecx, 15:8, desc9 , Descript= or #9 + 0x2, 0, ecx, 23:16, desc10 , Descript= or #10 + 0x2, 0, ecx, 30:24, desc11 , Descript= or #11 + 0x2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set + 0x2, 0, edx, 7:0, desc12 , Descript= or #12 + 0x2, 0, edx, 15:8, desc13 , Descript= or #13 + 0x2, 0, edx, 23:16, desc14 , Descript= or #14 + 0x2, 0, edx, 30:24, desc15 , Descript= or #15 + 0x2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + +# Leaf 3H +# Transmeta Processor Serial Number (PSN) + + 0x3, 0, eax, 31:0, cpu_psn_0 , Processo= r Serial Number bytes 0 - 3 + 0x3, 0, ebx, 31:0, cpu_psn_1 , Processo= r Serial Number bytes 4 - 7 + 0x3, 0, ecx, 31:0, cpu_psn_2 , Processo= r Serial Number bytes 8 - 11 + 0x3, 0, edx, 31:0, cpu_psn_3 , Processo= r Serial Number bytes 12 - 15 =20 # Leaf 4H # Intel deterministic cache parameters =20 - 4, 31:0, eax, 4:0, cache_type , Cache ty= pe field - 4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) - 4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level - 4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache - 4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache - 4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package - 4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) - 4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) - 4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) - 4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) - 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches - 4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches - 4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) + 0x4, 31:0, eax, 4:0, cache_type , Cache ty= pe field + 0x4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) + 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 0x4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache + 0x4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache + 0x4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package + 0x4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) + 0x4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) + 0x4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) + 0x4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) + 0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches + 0x4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches + 0x4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) =20 # Leaf 5H # MONITOR/MWAIT instructions enumeration =20 - 5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes - 5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes - 5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported - 5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported - 5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT - 5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT - 5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT - 5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT - 5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT - 5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT - 5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT - 5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT + 0x5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes + 0x5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes + 0x5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported + 0x5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported + 0x5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT + 0x5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT + 0x5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT + 0x5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT + 0x5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT + 0x5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT + 0x5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT + 0x5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT =20 # Leaf 6H # Thermal and Power Management enumeration =20 - 6, 0, eax, 0, dtherm , Digital = temprature sensor - 6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost - 6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) - 6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event - 6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension - 6, 0, eax, 6, pts , Package = thermal management - 6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported - 6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) - 6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported - 6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference - 6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request - 6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported - 6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 - 6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change - 6, 0, eax, 16, hwp_peci_override , HWP PECI= override - 6, 0, eax, 17, hwp_flexible , Flexible= HWP - 6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode - 6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported - 6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported - 6, 0, eax, 23, thread_director , Intel th= read director support - 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported - 6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds - 6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) - 6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support - 6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director - 6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting - 6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting - 6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages - 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + 0x6, 0, eax, 0, dtherm , Digital = temprature sensor + 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost + 0x6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) + 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event + 0x6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension + 0x6, 0, eax, 6, pts , Package = thermal management + 0x6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported + 0x6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) + 0x6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported + 0x6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference + 0x6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request + 0x6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported + 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 + 0x6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change + 0x6, 0, eax, 16, hwp_peci_override , HWP PECI= override + 0x6, 0, eax, 17, hwp_flexible , Flexible= HWP + 0x6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode + 0x6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported + 0x6, 0, eax, 23, thread_director , Intel th= read director support + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported + 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds + 0x6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) + 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support + 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director + 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting + 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting + 0x6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages + 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based =20 # Leaf 7H # Extended CPU features enumeration =20 - 7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves - 7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support - 7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported - 7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) - 7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 - 7, 0, ebx, 4, hle , Hardware= Lock Elision - 7, 0, ebx, 5, avx2 , AVX2 ins= truction set - 7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions - 7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection - 7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 - 7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB - 7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) - 7, 0, ebx, 11, rtm , Intel re= stricted transactional memory - 7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring - 7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) - 7, 0, ebx, 14, mpx , Intel me= mory protection extensions - 7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent - 7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions - 7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions - 7, 0, ebx, 18, rdseed , RDSEED i= nstruction - 7, 0, ebx, 19, adx , ADCX/ADO= X instructions - 7, 0, ebx, 20, smap , Supervis= or mode access prevention - 7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add - 7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction - 7, 0, ebx, 24, clwb , CLWB ins= truction - 7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace - 7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions - 7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs - 7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs - 7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions - 7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions - 7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions - 7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) - 7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs - 7, 0, ecx, 2, umip , User mod= e instruction protection - 7, 0, ecx, 3, pku , Protecti= on keys for user-space - 7, 0, ecx, 4, ospke , OS prote= ction keys enable - 7, 0, ecx, 5, waitpkg , WAITPKG = instructions - 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 - 7, 0, ecx, 7, cet_ss , CET shad= ow stack features - 7, 0, ecx, 8, gfni , Galois f= ield new instructions - 7, 0, ecx, 9, vaes , Vector A= ES instrs - 7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support - 7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions - 7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle - 7, 0, ecx, 13, tme , Intel to= tal memory encryption - 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW - 7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) - 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode - 7, 0, ecx, 22, rdpid , RDPID in= struction - 7, 0, ecx, 23, key_locker , Intel ke= y locker support - 7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection - 7, 0, ecx, 25, cldemote , CLDEMOTE= instruction - 7, 0, ecx, 27, movdiri , MOVDIRI = instruction - 7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction - 7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) - 7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration - 7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages - 7, 0, edx, 1, sgx_keys , Intel SG= X attestation services - 7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions - 7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision - 7, 0, edx, 4, fsrm , Fast sho= rt REP MOV - 7, 0, edx, 5, uintr , CPU supp= orts user interrupts - 7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions - 7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available - 7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support - 7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts - 7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported - 7, 0, edx, 14, serialize , SERIALIZ= E instruction - 7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' - 7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking - 7, 0, edx, 18, pconfig , PCONFIG = instruction - 7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs - 7, 0, edx, 20, ibt , CET indi= rect branch tracking - 7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support - 7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions - 7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support - 7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support - 7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) - 7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors - 7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR - 7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR - 7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR - 7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable - 7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions - 7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions - 7, 1, eax, 6, lass , Linear a= ddress space separation - 7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported - 7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB - 7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB - 7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB - 7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions - 7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS - 7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) - 7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations - 7, 1, eax, 22, hreset , History = reset support - 7, 1, eax, 23, avx_ifma , Integer = fused multiply add - 7, 1, eax, 26, lam , Linear a= ddress masking - 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions - 7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) - 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions - 7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions - 7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) - 7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions - 7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use - 7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable - 7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} - 7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} - 7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U - 7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S - 7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed - 7, 2, edx, 6, uclock_disable , UC-lock = disable is supported + 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported + 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) + 0x7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 + 0x7, 0, ebx, 4, hle , Hardware= Lock Elision + 0x7, 0, ebx, 5, avx2 , AVX2 ins= truction set + 0x7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions + 0x7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection + 0x7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 + 0x7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB + 0x7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) + 0x7, 0, ebx, 11, rtm , Intel re= stricted transactional memory + 0x7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring + 0x7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) + 0x7, 0, ebx, 14, mpx , Intel me= mory protection extensions + 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 0x7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions + 0x7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions + 0x7, 0, ebx, 18, rdseed , RDSEED i= nstruction + 0x7, 0, ebx, 19, adx , ADCX/ADO= X instructions + 0x7, 0, ebx, 20, smap , Supervis= or mode access prevention + 0x7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add + 0x7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction + 0x7, 0, ebx, 24, clwb , CLWB ins= truction + 0x7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace + 0x7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions + 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs + 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 0x7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions + 0x7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 0x7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions + 0x7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) + 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 0x7, 0, ecx, 2, umip , User mod= e instruction protection + 0x7, 0, ecx, 3, pku , Protecti= on keys for user-space + 0x7, 0, ecx, 4, ospke , OS prote= ction keys enable + 0x7, 0, ecx, 5, waitpkg , WAITPKG = instructions + 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features + 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions + 0x7, 0, ecx, 9, vaes , Vector A= ES instrs + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support + 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions + 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption + 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW + 0x7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode + 0x7, 0, ecx, 22, rdpid , RDPID in= struction + 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support + 0x7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection + 0x7, 0, ecx, 25, cldemote , CLDEMOTE= instruction + 0x7, 0, ecx, 27, movdiri , MOVDIRI = instruction + 0x7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction + 0x7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) + 0x7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration + 0x7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages + 0x7, 0, edx, 1, sgx_keys , Intel SG= X attestation services + 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions + 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision + 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOV + 0x7, 0, edx, 5, uintr , CPU supp= orts user interrupts + 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available + 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support + 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported + 0x7, 0, edx, 14, serialize , SERIALIZ= E instruction + 0x7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' + 0x7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking + 0x7, 0, edx, 18, pconfig , PCONFIG = instruction + 0x7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs + 0x7, 0, edx, 20, ibt , CET indi= rect branch tracking + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support + 0x7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions + 0x7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support + 0x7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support + 0x7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) + 0x7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors + 0x7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR + 0x7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR + 0x7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR + 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable + 0x7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions + 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 0x7, 1, eax, 6, lass , Linear a= ddress space separation + 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB + 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB + 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB + 0x7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions + 0x7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS + 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data + 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations + 0x7, 1, eax, 22, hreset , History = reset support + 0x7, 1, eax, 23, avx_ifma , Integer = fused multiply add + 0x7, 1, eax, 26, lam , Linear a= ddress masking + 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions + 0x7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) + 0x7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions + 0x7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions + 0x7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) + 0x7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions + 0x7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use + 0x7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable + 0x7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} + 0x7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U + 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S + 0x7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed + 0x7, 2, edx, 6, uclock_disable , UC-lock = disable is supported =20 # Leaf 9H # Intel DCA (Direct Cache Access) enumeration =20 - 9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS + 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS =20 # Leaf AH # Intel PMU (Performance Monitoring Unit) enumeration @@ -623,7 +632,7 @@ 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervis= or ID string bytes 8 - 11 =20 # Leaf 80000000H -# Maximum extended leaf number + CPU vendor string (AMD) +# Maximum extended leaf number + AMD/Transmeta CPU vendor string =20 0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 @@ -636,6 +645,7 @@ 0x80000001, 0, eax, 3:0, e_stepping_id , Stepping= ID 0x80000001, 0, eax, 7:4, e_base_model , Base pro= cessor model 0x80000001, 0, eax, 11:8, e_base_family , Base pro= cessor family +0x80000001, 0, eax, 13:12, e_base_type , Base pro= cessor type (Transmeta) 0x80000001, 0, eax, 19:16, e_ext_model , Extended= processor model 0x80000001, 0, eax, 27:20, e_ext_family , Extended= processor family 0x80000001, 0, ebx, 15:0, brand_id , Brand ID @@ -687,6 +697,7 @@ 0x80000001, 0, edx, 19, mp , Out-of-s= pec AMD Multiprocessing bit 0x80000001, 0, edx, 20, nx , No-execu= te page protection 0x80000001, 0, edx, 22, mmxext , AMD MMX = extensions +0x80000001, 0, edx, 23, e_mmx , MMX inst= ructions (Transmeta) 0x80000001, 0, edx, 24, e_fxsr , FXSAVE a= nd FXRSTOR instructions 0x80000001, 0, edx, 25, fxsr_opt , FXSAVE a= nd FXRSTOR optimizations 0x80000001, 0, edx, 26, pdpe1gb , 1-GB lar= ge page support @@ -720,7 +731,7 @@ 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU bran= d ID string, bytes 44 - 47 =20 # Leaf 80000005H -# AMD L1 cache and L1 TLB enumeration +# AMD/Transmeta L1 cache and L1 TLB enumeration =20 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages @@ -1051,3 +1062,108 @@ 0x80000026, 3:0, ecx, 7:0, domain_level , This dom= ain level (subleaf ID) 0x80000026, 3:0, ecx, 15:8, domain_type , This dom= ain type 0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU + +# Leaf 80860000H +# Maximum Transmeta leaf number + CPU vendor ID string + +0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = supported Transmeta leaf number +0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a Vendor ID string bytes 0 - 3 +0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a Vendor ID string bytes 8 - 11 +0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a Vendor ID string bytes 4 - 7 + +# Leaf 80860001H +# Transmeta extended CPU information + +0x80860001, 0, eax, 3:0, stepping , Stepping= ID +0x80860001, 0, eax, 7:4, base_model , Base CPU= model ID +0x80860001, 0, eax, 11:8, base_family_id , Base CPU= family ID +0x80860001, 0, eax, 13:12, cpu_type , CPU type +0x80860001, 0, ebx, 7:0, cpu_rev_mask_minor , CPU revi= sion ID, mask minor +0x80860001, 0, ebx, 15:8, cpu_rev_mask_major , CPU revi= sion ID, mask major +0x80860001, 0, ebx, 23:16, cpu_rev_minor , CPU revi= sion ID, minor +0x80860001, 0, ebx, 31:24, cpu_rev_major , CPU revi= sion ID, major +0x80860001, 0, ecx, 31:0, cpu_base_mhz , CPU nomi= nal frequency, in MHz +0x80860001, 0, edx, 0, recovery , Recovery= CMS is active (after bad flush) +0x80860001, 0, edx, 1, longrun , LongRun = power management capabilities +0x80860001, 0, edx, 3, lrti , LongRun = Table Interface + +# Leaf 80860002H +# Transmeta Code Morphing Software (CMS) enumeration + +0x80860002, 0, eax, 31:0, cpu_rev_id , CPU revi= sion ID +0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revi= sion ID, mask component 2 +0x80860002, 0, ebx, 15:8, cms_rev_mask_1 , CMS revi= sion ID, mask component 1 +0x80860002, 0, ebx, 23:16, cms_rev_minor , CMS revi= sion ID, minor +0x80860002, 0, ebx, 31:24, cms_rev_major , CMS revi= sion ID, major +0x80860002, 0, ecx, 31:0, cms_rev_mask_3 , CMS revi= sion ID, mask component 3 + +# Leaf 80860003H +# Transmeta CPU information string, bytes 0 - 15 + +0x80860003, 0, eax, 31:0, cpu_info_0 , CPU info= string bytes 0 - 3 +0x80860003, 0, ebx, 31:0, cpu_info_1 , CPU info= string bytes 4 - 7 +0x80860003, 0, ecx, 31:0, cpu_info_2 , CPU info= string bytes 8 - 11 +0x80860003, 0, edx, 31:0, cpu_info_3 , CPU info= string bytes 12 - 15 + +# Leaf 80860004H +# Transmeta CPU information string, bytes 16 - 31 + +0x80860004, 0, eax, 31:0, cpu_info_4 , CPU info= string bytes 16 - 19 +0x80860004, 0, ebx, 31:0, cpu_info_5 , CPU info= string bytes 20 - 23 +0x80860004, 0, ecx, 31:0, cpu_info_6 , CPU info= string bytes 24 - 27 +0x80860004, 0, edx, 31:0, cpu_info_7 , CPU info= string bytes 28 - 31 + +# Leaf 80860005H +# Transmeta CPU information string, bytes 32 - 47 + +0x80860005, 0, eax, 31:0, cpu_info_8 , CPU info= string bytes 32 - 35 +0x80860005, 0, ebx, 31:0, cpu_info_9 , CPU info= string bytes 36 - 39 +0x80860005, 0, ecx, 31:0, cpu_info_10 , CPU info= string bytes 40 - 43 +0x80860005, 0, edx, 31:0, cpu_info_11 , CPU info= string bytes 44 - 47 + +# Leaf 80860006H +# Transmeta CPU information string, bytes 48 - 63 + +0x80860006, 0, eax, 31:0, cpu_info_12 , CPU info= string bytes 48 - 51 +0x80860006, 0, ebx, 31:0, cpu_info_13 , CPU info= string bytes 52 - 55 +0x80860006, 0, ecx, 31:0, cpu_info_14 , CPU info= string bytes 56 - 59 +0x80860006, 0, edx, 31:0, cpu_info_15 , CPU info= string bytes 60 - 63 + +# Leaf 80860007H +# Transmeta live CPU information + +0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current = CPU frequency, in MHz +0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current = CPU voltage, in millivolts +0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100d +0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current = CPU gate delay, in femtoseconds + +# Leaf C0000000H +# Maximum Centaur/Zhaoxin leaf number + +0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum = Centaur/Zhaoxin leaf number + +# Leaf C0000001H +# Centaur/Zhaoxin extended CPU features + +0xc0000001, 0, edx, 0, ccs_sm2 , CCS SM2 = instructions +0xc0000001, 0, edx, 1, ccs_sm2_en , CCS SM2 = enabled +0xc0000001, 0, edx, 2, xstore , Random N= umber Generator +0xc0000001, 0, edx, 3, xstore_en , RNG enab= led +0xc0000001, 0, edx, 4, ccs_sm3_sm4 , CCS SM3 = and SM4 instructions +0xc0000001, 0, edx, 5, ccs_sm3_sm4_en , CCS SM3/= SM4 enabled +0xc0000001, 0, edx, 6, ace , Advanced= Cryptography Engine +0xc0000001, 0, edx, 7, ace_en , ACE enab= led +0xc0000001, 0, edx, 8, ace2 , Advanced= Cryptography Engine v2 +0xc0000001, 0, edx, 9, ace2_en , ACE v2 e= nabled +0xc0000001, 0, edx, 10, phe , PadLock = Hash Engine +0xc0000001, 0, edx, 11, phe_en , PHE enab= led +0xc0000001, 0, edx, 12, pmm , PadLock = Montgomery Multiplier +0xc0000001, 0, edx, 13, pmm_en , PMM enab= led +0xc0000001, 0, edx, 16, parallax , Parallax= auto adjust processor voltage +0xc0000001, 0, edx, 17, parallax_en , Parallax= enabled +0xc0000001, 0, edx, 20, tm3 , Thermal = Monitor v3 +0xc0000001, 0, edx, 21, tm3_en , TM v3 en= abled +0xc0000001, 0, edx, 25, phe2 , PadLock = Hash Engine v2 (SHA384/SHA512) +0xc0000001, 0, edx, 26, phe2_en , PHE v2 e= nabled +0xc0000001, 0, edx, 27, rsa , RSA inst= ructions (XMODEXP/MONTMUL2) +0xc0000001, 0, edx, 28, rsa_en , RSA inst= ructions enabled --=20 2.48.1