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([82.78.167.46]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fdbcfaasm120146525e9.35.2025.03.24.06.57.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Mar 2025 06:57:10 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH v3 1/4] dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit Date: Mon, 24 Mar 2025 15:56:58 +0200 Message-ID: <20250324135701.179827-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> References: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The temperature is measured using the RZ/G3S ADC, with a dedicated ADC channel directly connected to the TSU. Add documentation for it. Reviewed-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected tags .../thermal/renesas,r9a08g045-tsu.yaml | 93 +++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/renesas,r9a08= g045-tsu.yaml diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-ts= u.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.ya= ml new file mode 100644 index 000000000000..573e2b9d3752 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a08g045-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S Thermal Sensor Unit + +description: + The thermal sensor unit (TSU) measures the temperature(Tj) inside + the LSI. + +maintainers: + - Claudiu Beznea + +$ref: thermal-sensor.yaml# + +properties: + compatible: + const: renesas,r9a08g045-tsu + + reg: + maxItems: 1 + + clocks: + items: + - description: TSU module clock + + power-domains: + maxItems: 1 + + resets: + items: + - description: TSU module reset + + io-channels: + items: + - description: ADC channel which reports the TSU temperature + + io-channel-names: + items: + - const: tsu + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - io-channels + - io-channel-names + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + #include + + tsu: thermal@10059000 { + compatible =3D "renesas,r9a08g045-tsu"; + reg =3D <0x10059000 0x1000>; + clocks =3D <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets =3D <&cpg R9A08G045_TSU_PRESETN>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + io-channels =3D <&adc 8>; + io-channel-names =3D "tsu"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsu>; + + trips { + sensor_crit: sensor-crit { + temperature =3D <125000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + target: trip-point { + temperature =3D <100000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; --=20 2.43.0 From nobody Thu Dec 18 14:43:27 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98C6825E82C for ; Mon, 24 Mar 2025 13:57:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([82.78.167.46]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fdbcfaasm120146525e9.35.2025.03.24.06.57.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Mar 2025 06:57:12 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH v3 2/4] thermal: renesas: rzg3s: Add thermal driver for the Renesas RZ/G3S SoC Date: Mon, 24 Mar 2025 15:56:59 +0200 Message-ID: <20250324135701.179827-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> References: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC features a Thermal Sensor Unit (TSU) that reports the junction temperature. The temperature is reported through a dedicated ADC channel. Add a driver for the Renesas RZ/G3S TSU. Signed-off-by: Claudiu Beznea --- Changes in v3: - drop the runtime resume/suspend from rzg3s_thermal_get_temp(); this is not needed as the temperature is read with ADC - opened the devres group id in rzg3s_thermal_probe() and rename previsouly rzg3s_thermal_probe() to rzg3s_thermal_probe_helper(), to have simpler code; this approach was suggested by Jonathan in [1]; as there is no positive feedback for the generic solution [2] this looks currently the best approach [1] https://lore.kernel.org/all/20250224120608.1769039-2-claudiu.beznea.uj@= bp.renesas.com [2] https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@b= p.renesas.com Changes in v2: - use a devres group for the devm resources obtained though this driver to avoid issue described in [1]; with this dropped the following calls: -- thermal_add_hwmon_sysfs(priv->tz); -- thermal_of_zone_register(priv->tz); -- pm_runtime_enable(priv->dev); and use devm variants - used signed variables for temperature computation - convert to mili degree Celsius before applying the computation formula to avoid losing precision [1] https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@b= p.renesas.com/ MAINTAINERS | 7 + drivers/thermal/renesas/Kconfig | 8 + drivers/thermal/renesas/Makefile | 1 + drivers/thermal/renesas/rzg3s_thermal.c | 313 ++++++++++++++++++++++++ 4 files changed, 329 insertions(+) create mode 100644 drivers/thermal/renesas/rzg3s_thermal.c diff --git a/MAINTAINERS b/MAINTAINERS index 7a9b8fa5f032..f3795fbcdcba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20594,6 +20594,13 @@ S: Maintained F: Documentation/devicetree/bindings/iio/potentiometer/renesas,x9250.yaml F: drivers/iio/potentiometer/x9250.c =20 +RENESAS RZ/G3S THERMAL SENSOR UNIT DRIVER +M: Claudiu Beznea +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml +F: drivers/thermal/renesas/rzg3s_thermal.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel S: Maintained diff --git a/drivers/thermal/renesas/Kconfig b/drivers/thermal/renesas/Kcon= fig index dcf5fc5ae08e..566478797095 100644 --- a/drivers/thermal/renesas/Kconfig +++ b/drivers/thermal/renesas/Kconfig @@ -26,3 +26,11 @@ config RZG2L_THERMAL help Enable this to plug the RZ/G2L thermal sensor driver into the Linux thermal framework. + +config RZG3S_THERMAL + tristate "Renesas RZ/G3S thermal driver" + depends on ARCH_R9A08G045 || COMPILE_TEST + depends on OF && IIO && RZG2L_ADC + help + Enable this to plug the RZ/G3S thermal sensor driver into the Linux + thermal framework. diff --git a/drivers/thermal/renesas/Makefile b/drivers/thermal/renesas/Mak= efile index bf9cb3cb94d6..1feb5ab78827 100644 --- a/drivers/thermal/renesas/Makefile +++ b/drivers/thermal/renesas/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_RCAR_GEN3_THERMAL) +=3D rcar_gen3_thermal.o obj-$(CONFIG_RCAR_THERMAL) +=3D rcar_thermal.o obj-$(CONFIG_RZG2L_THERMAL) +=3D rzg2l_thermal.o +obj-$(CONFIG_RZG3S_THERMAL) +=3D rzg3s_thermal.o diff --git a/drivers/thermal/renesas/rzg3s_thermal.c b/drivers/thermal/rene= sas/rzg3s_thermal.c new file mode 100644 index 000000000000..e0bc51943875 --- /dev/null +++ b/drivers/thermal/renesas/rzg3s_thermal.c @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3S TSU Thermal Sensor Driver + * + * Copyright (C) 2024 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +#define TSU_SM 0x0 +#define TSU_SM_EN BIT(0) +#define TSU_SM_OE BIT(1) +#define OTPTSUTRIM_REG(n) (0x18 + (n) * 0x4) +#define OTPTSUTRIM_EN_MASK BIT(31) +#define OTPTSUTRIM_MASK GENMASK(11, 0) + +#define TSU_READ_STEPS 8 + +/* Default calibration values, if FUSE values are missing. */ +#define SW_CALIB0_VAL 1297 +#define SW_CALIB1_VAL 751 + +#define MCELSIUS(temp) ((temp) * MILLIDEGREE_PER_DEGREE) + +/** + * struct rzg3s_thermal_priv - RZ/G3S thermal private data structure + * @base: TSU base address + * @dev: device pointer + * @tz: thermal zone pointer + * @rstc: reset control + * @channel: IIO channel to read the TSU + * @devres_group_id: devres group for the driver devres resources + * obtained in probe + * @mode: current device mode + * @calib0: calibration value + * @calib1: calibration value + */ +struct rzg3s_thermal_priv { + void __iomem *base; + struct device *dev; + struct thermal_zone_device *tz; + struct reset_control *rstc; + struct iio_channel *channel; + void *devres_group_id; + enum thermal_device_mode mode; + u16 calib0; + u16 calib1; +}; + +static int rzg3s_thermal_get_temp(struct thermal_zone_device *tz, int *tem= p) +{ + struct rzg3s_thermal_priv *priv =3D thermal_zone_device_priv(tz); + int ts_code_ave =3D 0; + int ret, val; + + if (priv->mode !=3D THERMAL_DEVICE_ENABLED) + return -EAGAIN; + + for (u8 i =3D 0; i < TSU_READ_STEPS; i++) { + ret =3D iio_read_channel_raw(priv->channel, &val); + if (ret < 0) + return ret; + + ts_code_ave +=3D val; + /* + * According to the HW manual (section 40.4.4 Procedure for Measuring the + * Temperature) we need to wait here at leat 3us. + */ + usleep_range(5, 10); + } + + ret =3D 0; + ts_code_ave =3D DIV_ROUND_CLOSEST(MCELSIUS(ts_code_ave), TSU_READ_STEPS); + + /* + * According to the HW manual (section 40.4.4 Procedure for Measuring the= Temperature) + * the computation formula is as follows: + * + * Tj =3D (ts_code_ave - priv->calib1) * 165 / (priv->calib0 - priv->cali= b1) - 40 + * + * Convert everything to mili Celsius before applying the formula to avoid + * losing precision. + */ + + *temp =3D DIV_ROUND_CLOSEST((s64)(ts_code_ave - MCELSIUS(priv->calib1)) *= MCELSIUS(165), + MCELSIUS(priv->calib0 - priv->calib1)) - MCELSIUS(40); + + /* Report it in mili degrees Celsius and round it up to 0.5 degrees Celsi= us. */ + *temp =3D roundup(*temp, 500); + + return ret; +} + +static void rzg3s_thermal_set_mode(struct rzg3s_thermal_priv *priv, + enum thermal_device_mode mode) +{ + struct device *dev =3D priv->dev; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return; + + if (mode =3D=3D THERMAL_DEVICE_DISABLED) { + writel(0, priv->base + TSU_SM); + } else { + writel(TSU_SM_EN, priv->base + TSU_SM); + /* + * According to the HW manual (section 40.4.1 Procedure for + * Starting the TSU) we need to wait here 30us or more. + */ + usleep_range(30, 40); + + writel(TSU_SM_OE | TSU_SM_EN, priv->base + TSU_SM); + /* + * According to the HW manual (section 40.4.1 Procedure for + * Starting the TSU) we need to wait here 50us or more. + */ + usleep_range(50, 60); + } + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); +} + +static int rzg3s_thermal_change_mode(struct thermal_zone_device *tz, + enum thermal_device_mode mode) +{ + struct rzg3s_thermal_priv *priv =3D thermal_zone_device_priv(tz); + + if (priv->mode =3D=3D mode) + return 0; + + rzg3s_thermal_set_mode(priv, mode); + priv->mode =3D mode; + + return 0; +} + +static const struct thermal_zone_device_ops rzg3s_tz_of_ops =3D { + .get_temp =3D rzg3s_thermal_get_temp, + .change_mode =3D rzg3s_thermal_change_mode, +}; + +static int rzg3s_thermal_read_calib(struct rzg3s_thermal_priv *priv) +{ + struct device *dev =3D priv->dev; + u32 val; + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + val =3D readl(priv->base + OTPTSUTRIM_REG(0)); + if (val & OTPTSUTRIM_EN_MASK) + priv->calib0 =3D FIELD_GET(OTPTSUTRIM_MASK, val); + else + priv->calib0 =3D SW_CALIB0_VAL; + + val =3D readl(priv->base + OTPTSUTRIM_REG(1)); + if (val & OTPTSUTRIM_EN_MASK) + priv->calib1 =3D FIELD_GET(OTPTSUTRIM_MASK, val); + else + priv->calib1 =3D SW_CALIB1_VAL; + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return 0; +} + +static int rzg3s_thermal_probe_helper(struct platform_device *pdev, void *= devres_group_id) +{ + struct rzg3s_thermal_priv *priv; + struct device *dev =3D &pdev->dev; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->devres_group_id =3D devres_group_id; + + priv->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->channel =3D devm_iio_channel_get(dev, "tsu"); + if (IS_ERR(priv->channel)) + return dev_err_probe(dev, PTR_ERR(priv->channel), "Failed to get IIO cha= nnel!\n"); + + priv->rstc =3D devm_reset_control_get_exclusive_deasserted(dev, NULL); + if (IS_ERR(priv->rstc)) + return dev_err_probe(dev, PTR_ERR(priv->rstc), "Failed to get reset!\n"); + + priv->dev =3D dev; + priv->mode =3D THERMAL_DEVICE_DISABLED; + platform_set_drvdata(pdev, priv); + + pm_runtime_set_autosuspend_delay(dev, 300); + pm_runtime_use_autosuspend(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable runtime PM!\n"); + + ret =3D rzg3s_thermal_read_calib(priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to read calibration data!\n"); + + priv->tz =3D devm_thermal_of_zone_register(dev, 0, priv, &rzg3s_tz_of_ops= ); + if (IS_ERR(priv->tz)) + return dev_err_probe(dev, PTR_ERR(priv->tz), "Failed to register thermal= zone!\n"); + + ret =3D devm_thermal_add_hwmon_sysfs(dev, priv->tz); + if (ret) + return dev_err_probe(dev, ret, "Failed to add hwmon sysfs!\n"); + + return 0; +} + +static int rzg3s_thermal_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + void *devres_group_id; + int ret; + + /* + * Open a devres group to allow using devm_pm_runtime_enable() + * w/o interfeering with dev_pm_genpd_detach() in the platform bus + * remove. Otherwise, durring repeated unbind/bind operations, + * the TSU may be runtime resumed when it is not part of its power + * domain, leading to accessing TSU registers (through + * rzg3s_thermal_change_mode()) without its clocks being enabled + * and its PM domain being turned on. + */ + devres_group_id =3D devres_open_group(dev, NULL, GFP_KERNEL); + if (!devres_group_id) + return -ENOMEM; + + ret =3D rzg3s_thermal_probe_helper(pdev, devres_group_id); + if (ret) + devres_release_group(dev, devres_group_id); + + return ret; +} + +static void rzg3s_thermal_remove(struct platform_device *pdev) +{ + struct rzg3s_thermal_priv *priv =3D dev_get_drvdata(&pdev->dev); + + devres_release_group(priv->dev, priv->devres_group_id); +} + +static int rzg3s_thermal_suspend(struct device *dev) +{ + struct rzg3s_thermal_priv *priv =3D dev_get_drvdata(dev); + + rzg3s_thermal_set_mode(priv, THERMAL_DEVICE_DISABLED); + + return reset_control_assert(priv->rstc); +} + +static int rzg3s_thermal_resume(struct device *dev) +{ + struct rzg3s_thermal_priv *priv =3D dev_get_drvdata(dev); + int ret; + + ret =3D reset_control_deassert(priv->rstc); + if (ret) + return ret; + + if (priv->mode !=3D THERMAL_DEVICE_DISABLED) + rzg3s_thermal_set_mode(priv, priv->mode); + + return 0; +} + +static const struct dev_pm_ops rzg3s_thermal_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(rzg3s_thermal_suspend, rzg3s_thermal_resume) +}; + +static const struct of_device_id rzg3s_thermal_dt_ids[] =3D { + { .compatible =3D "renesas,r9a08g045-tsu" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzg3s_thermal_dt_ids); + +static struct platform_driver rzg3s_thermal_driver =3D { + .driver =3D { + .name =3D "rzg3s_thermal", + .of_match_table =3D rzg3s_thermal_dt_ids, + .pm =3D pm_ptr(&rzg3s_thermal_pm_ops), + }, + .probe =3D rzg3s_thermal_probe, + .remove =3D rzg3s_thermal_remove, +}; +module_platform_driver(rzg3s_thermal_driver); + +MODULE_DESCRIPTION("Renesas RZ/G3S Thermal Sensor Unit Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Thu Dec 18 14:43:27 2025 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DDC125F994 for ; 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([82.78.167.46]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fdbcfaasm120146525e9.35.2025.03.24.06.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Mar 2025 06:57:14 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH v3 3/4] arm64: dts: renesas: r9a08g045: Add TSU node Date: Mon, 24 Mar 2025 15:57:00 +0200 Message-ID: <20250324135701.179827-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> References: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add TSU node along with thermal zones and keep it enabled in the SoC DTSI. The temperature reported by the TSU can only be read through channel 8 of the ADC. Therefore, enable the ADC by default. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected Geert's tag - adjusted the trip points temperature as suggested in the review process - added cpu_alert1 passive trip point as suggested in the review process; along with it changed the trip point nodes and label names Hi, Geert, I kept your Rb tag. Please let me know if it should be dropped. Thank you, Claudiu arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 49 ++++++++++++++++++- .../boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 -- 2 files changed, 48 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 0364f89776e6..3f56fff7d9b0 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -233,7 +233,6 @@ adc: adc@10058000 { #address-cells =3D <1>; #size-cells =3D <0>; #io-channel-cells =3D <1>; - status =3D "disabled"; =20 channel@0 { reg =3D <0>; @@ -272,6 +271,17 @@ channel@8 { }; }; =20 + tsu: thermal@10059000 { + compatible =3D "renesas,r9a08g045-tsu"; + reg =3D <0 0x10059000 0 0x1000>; + clocks =3D <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets =3D <&cpg R9A08G045_TSU_PRESETN>; + power-domains =3D <&cpg>; + #thermal-sensor-cells =3D <0>; + io-channels =3D <&adc 8>; + io-channel-names =3D "tsu"; + }; + vbattb: clock-controller@1005c000 { compatible =3D "renesas,r9a08g045-vbattb"; reg =3D <0 0x1005c000 0 0x1000>; @@ -717,6 +727,43 @@ timer { "hyp-virt"; }; =20 + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsu>; + sustainable-power =3D <423>; + + cooling-maps { + map0 { + trip =3D <&cpu_alert0>; + cooling-device =3D <&cpu0 0 2>; + contribution =3D <1024>; + }; + }; + + trips { + cpu_crit: cpu-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + + cpu_alert1: trip-point1 { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + cpu_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + }; + }; + }; + vbattb_xtal: vbattb-xtal { compatible =3D "fixed-clock"; #clock-cells =3D <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 39845faec894..6f25ab617982 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -84,10 +84,6 @@ x3_clk: x3-clock { }; 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([82.78.167.46]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d4fdbcfaasm120146525e9.35.2025.03.24.06.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Mar 2025 06:57:16 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: rafael@kernel.org, daniel.lezcano@linaro.org, rui.zhang@intel.com, lukasz.luba@arm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH v3 4/4] arm64: defconfig: Enable RZ/G3S thermal Date: Mon, 24 Mar 2025 15:57:01 +0200 Message-ID: <20250324135701.179827-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> References: <20250324135701.179827-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable the CONFIG_RZG3S_THERMAL flag for the RZ/G3S SoC. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected tags arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5bb8f09422a2..79e566f0d47f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -715,6 +715,7 @@ CONFIG_ROCKCHIP_THERMAL=3Dm CONFIG_RCAR_THERMAL=3Dy CONFIG_RCAR_GEN3_THERMAL=3Dy CONFIG_RZG2L_THERMAL=3Dy +CONFIG_RZG3S_THERMAL=3Dm CONFIG_ARMADA_THERMAL=3Dy CONFIG_MTK_THERMAL=3Dm CONFIG_MTK_LVTS_THERMAL=3Dm --=20 2.43.0