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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 07/29] x86/cacheinfo: Use proper name for cacheinfo instances Date: Mon, 24 Mar 2025 14:33:02 +0100 Message-ID: <20250324133324.23458-8-darwi@linutronix.de> In-Reply-To: <20250324133324.23458-1-darwi@linutronix.de> References: <20250324133324.23458-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner The cacheinfo structure defined at is a generic cache info object representation. Calling its instances at x86 cacheinfo.c "leaf" confuses it with a CPUID leaf -- especially that multiple CPUID calls are already sprinkled across that file. Most of such instances also have a redundant "this_" prefix. Rename all of the cacheinfo "this_leaf" instances to just "ci". [ darwi: Move into separate commit and write commit log ] Signed-off-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 89 ++++++++++++++++----------------- 1 file changed, 43 insertions(+), 46 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 0fd4e9673665..be9be5e56b44 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -349,11 +349,10 @@ static int amd_get_l3_disable_slot(struct amd_northbr= idge *nb, unsigned slot) return -1; } =20 -static ssize_t show_cache_disable(struct cacheinfo *this_leaf, char *buf, - unsigned int slot) +static ssize_t show_cache_disable(struct cacheinfo *ci, char *buf, unsigne= d int slot) { int index; - struct amd_northbridge *nb =3D this_leaf->priv; + struct amd_northbridge *nb =3D ci->priv; =20 index =3D amd_get_l3_disable_slot(nb, slot); if (index >=3D 0) @@ -367,8 +366,8 @@ static ssize_t \ cache_disable_##slot##_show(struct device *dev, \ struct device_attribute *attr, char *buf) \ { \ - struct cacheinfo *this_leaf =3D dev_get_drvdata(dev); \ - return show_cache_disable(this_leaf, buf, slot); \ + struct cacheinfo *ci =3D dev_get_drvdata(dev); \ + return show_cache_disable(ci, buf, slot); \ } SHOW_CACHE_DISABLE(0) SHOW_CACHE_DISABLE(1) @@ -435,18 +434,17 @@ static int amd_set_l3_disable_slot(struct amd_northbr= idge *nb, int cpu, return 0; } =20 -static ssize_t store_cache_disable(struct cacheinfo *this_leaf, - const char *buf, size_t count, - unsigned int slot) +static ssize_t store_cache_disable(struct cacheinfo *ci, const char *buf, + size_t count, unsigned int slot) { unsigned long val =3D 0; int cpu, err =3D 0; - struct amd_northbridge *nb =3D this_leaf->priv; + struct amd_northbridge *nb =3D ci->priv; =20 if (!capable(CAP_SYS_ADMIN)) return -EPERM; =20 - cpu =3D cpumask_first(&this_leaf->shared_cpu_map); + cpu =3D cpumask_first(&ci->shared_cpu_map); =20 if (kstrtoul(buf, 10, &val) < 0) return -EINVAL; @@ -467,8 +465,8 @@ cache_disable_##slot##_store(struct device *dev, \ struct device_attribute *attr, \ const char *buf, size_t count) \ { \ - struct cacheinfo *this_leaf =3D dev_get_drvdata(dev); \ - return store_cache_disable(this_leaf, buf, count, slot); \ + struct cacheinfo *ci =3D dev_get_drvdata(dev); \ + return store_cache_disable(ci, buf, count, slot); \ } STORE_CACHE_DISABLE(0) STORE_CACHE_DISABLE(1) @@ -476,8 +474,8 @@ STORE_CACHE_DISABLE(1) static ssize_t subcaches_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct cacheinfo *this_leaf =3D dev_get_drvdata(dev); - int cpu =3D cpumask_first(&this_leaf->shared_cpu_map); + struct cacheinfo *ci =3D dev_get_drvdata(dev); + int cpu =3D cpumask_first(&ci->shared_cpu_map); =20 return sprintf(buf, "%x\n", amd_get_subcaches(cpu)); } @@ -486,8 +484,8 @@ static ssize_t subcaches_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - struct cacheinfo *this_leaf =3D dev_get_drvdata(dev); - int cpu =3D cpumask_first(&this_leaf->shared_cpu_map); + struct cacheinfo *ci =3D dev_get_drvdata(dev); + int cpu =3D cpumask_first(&ci->shared_cpu_map); unsigned long val; =20 if (!capable(CAP_SYS_ADMIN)) @@ -511,10 +509,10 @@ cache_private_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int unused) { struct device *dev =3D kobj_to_dev(kobj); - struct cacheinfo *this_leaf =3D dev_get_drvdata(dev); + struct cacheinfo *ci =3D dev_get_drvdata(dev); umode_t mode =3D attr->mode; =20 - if (!this_leaf->priv) + if (!ci->priv) return 0; =20 if ((attr =3D=3D &dev_attr_subcaches.attr) && @@ -562,11 +560,11 @@ static void init_amd_l3_attrs(void) } =20 const struct attribute_group * -cache_get_priv_group(struct cacheinfo *this_leaf) +cache_get_priv_group(struct cacheinfo *ci) { - struct amd_northbridge *nb =3D this_leaf->priv; + struct amd_northbridge *nb =3D ci->priv; =20 - if (this_leaf->level < 3 || !nb) + if (ci->level < 3 || !nb) return NULL; =20 if (nb && nb->l3_cache.indices) @@ -846,7 +844,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, struct _cpuid4_info_regs *base) { struct cpu_cacheinfo *this_cpu_ci; - struct cacheinfo *this_leaf; + struct cacheinfo *ci; int i, sibling; =20 /* @@ -858,12 +856,12 @@ static int __cache_amd_cpumap_setup(unsigned int cpu,= int index, this_cpu_ci =3D get_cpu_cacheinfo(i); if (!this_cpu_ci->info_list) continue; - this_leaf =3D this_cpu_ci->info_list + index; + ci =3D this_cpu_ci->info_list + index; for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) { if (!cpu_online(sibling)) continue; cpumask_set_cpu(sibling, - &this_leaf->shared_cpu_map); + &ci->shared_cpu_map); } } } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { @@ -883,14 +881,14 @@ static int __cache_amd_cpumap_setup(unsigned int cpu,= int index, if ((apicid < first) || (apicid > last)) continue; =20 - this_leaf =3D this_cpu_ci->info_list + index; + ci =3D this_cpu_ci->info_list + index; =20 for_each_online_cpu(sibling) { apicid =3D cpu_data(sibling).topo.apicid; if ((apicid < first) || (apicid > last)) continue; cpumask_set_cpu(sibling, - &this_leaf->shared_cpu_map); + &ci->shared_cpu_map); } } } else @@ -903,7 +901,7 @@ static void __cache_cpumap_setup(unsigned int cpu, int = index, struct _cpuid4_info_regs *base) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); - struct cacheinfo *this_leaf, *sibling_leaf; + struct cacheinfo *ci, *sibling_ci; unsigned long num_threads_sharing; int index_msb, i; struct cpuinfo_x86 *c =3D &cpu_data(cpu); @@ -914,10 +912,10 @@ static void __cache_cpumap_setup(unsigned int cpu, in= t index, return; } =20 - this_leaf =3D this_cpu_ci->info_list + index; + ci =3D this_cpu_ci->info_list + index; num_threads_sharing =3D 1 + base->eax.split.num_threads_sharing; =20 - cpumask_set_cpu(cpu, &this_leaf->shared_cpu_map); + cpumask_set_cpu(cpu, &ci->shared_cpu_map); if (num_threads_sharing =3D=3D 1) return; =20 @@ -929,28 +927,27 @@ static void __cache_cpumap_setup(unsigned int cpu, in= t index, =20 if (i =3D=3D cpu || !sib_cpu_ci->info_list) continue;/* skip if itself or no cacheinfo */ - sibling_leaf =3D sib_cpu_ci->info_list + index; - cpumask_set_cpu(i, &this_leaf->shared_cpu_map); - cpumask_set_cpu(cpu, &sibling_leaf->shared_cpu_map); + sibling_ci =3D sib_cpu_ci->info_list + index; + cpumask_set_cpu(i, &ci->shared_cpu_map); + cpumask_set_cpu(cpu, &sibling_ci->shared_cpu_map); } } =20 -static void ci_leaf_init(struct cacheinfo *this_leaf, - struct _cpuid4_info_regs *base) +static void ci_info_init(struct cacheinfo *ci, struct _cpuid4_info_regs *b= ase) { - this_leaf->id =3D base->id; - this_leaf->attributes =3D CACHE_ID; - this_leaf->level =3D base->eax.split.level; - this_leaf->type =3D cache_type_map[base->eax.split.type]; - this_leaf->coherency_line_size =3D + ci->id =3D base->id; + ci->attributes =3D CACHE_ID; + ci->level =3D base->eax.split.level; + ci->type =3D cache_type_map[base->eax.split.type]; + ci->coherency_line_size =3D base->ebx.split.coherency_line_size + 1; - this_leaf->ways_of_associativity =3D + ci->ways_of_associativity =3D base->ebx.split.ways_of_associativity + 1; - this_leaf->size =3D base->size; - this_leaf->number_of_sets =3D base->ecx.split.number_of_sets + 1; - this_leaf->physical_line_partition =3D + ci->size =3D base->size; + ci->number_of_sets =3D base->ecx.split.number_of_sets + 1; + ci->physical_line_partition =3D base->ebx.split.physical_line_partition + 1; - this_leaf->priv =3D base->nb; + ci->priv =3D base->nb; } =20 int init_cache_level(unsigned int cpu) @@ -984,7 +981,7 @@ int populate_cache_leaves(unsigned int cpu) { unsigned int idx, ret; struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); - struct cacheinfo *this_leaf =3D this_cpu_ci->info_list; + struct cacheinfo *ci =3D this_cpu_ci->info_list; struct _cpuid4_info_regs id4_regs =3D {}; =20 for (idx =3D 0; idx < this_cpu_ci->num_leaves; idx++) { @@ -992,7 +989,7 @@ int populate_cache_leaves(unsigned int cpu) if (ret) return ret; get_cache_id(cpu, &id4_regs); - ci_leaf_init(this_leaf++, &id4_regs); + ci_info_init(ci++, &id4_regs); __cache_cpumap_setup(cpu, idx, &id4_regs); } this_cpu_ci->cpu_map_populated =3D true; --=20 2.48.1