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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v4 04/29] x86/cacheinfo: Use leaf 0x2 parsing helpers Date: Mon, 24 Mar 2025 14:32:59 +0100 Message-ID: <20250324133324.23458-5-darwi@linutronix.de> In-Reply-To: <20250324133324.23458-1-darwi@linutronix.de> References: <20250324133324.23458-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parent commit introduced CPUID leaf 0x2 parsing helpers at . The new API allows sharing leaf 0x2's output validation and iteration logic across both intel.c and cacheinfo.c. Convert cacheinfo.c to that new API. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 36782fd017b3..6c610805e356 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -783,29 +784,16 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) =20 /* Don't use CPUID(2) if CPUID(4) is supported. */ if (!ci->num_leaves && c->cpuid_level > 1) { - u32 regs[4]; - u8 *desc =3D (u8 *)regs; + union leaf_0x2_regs regs; + u8 *desc; =20 - cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]); - - /* Intel CPUs must report an iteration count of 1 */ - if (desc[0] !=3D 0x01) - return; - - /* If a register's bit 31 is set, it is an unknown format */ - for (int i =3D 0; i < 4; i++) { - if (regs[i] & (1 << 31)) - regs[i] =3D 0; - } - - /* Skip the first byte as it is not a descriptor */ - for (int i =3D 1; i < 16; i++) { - u8 des =3D desc[i]; + cpuid_get_leaf_0x2_regs(®s); + for_each_leaf_0x2_desc(regs, desc) { u8 k =3D 0; =20 /* look up this descriptor in the table */ while (cache_table[k].descriptor !=3D 0) { - if (cache_table[k].descriptor =3D=3D des) { + if (cache_table[k].descriptor =3D=3D *desc) { switch (cache_table[k].cache_type) { case LVL_1_INST: l1i +=3D cache_table[k].size; --=20 2.48.1