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Link: https://www.cixtech.com/. Acked-by: Krzysztof Kozlowski Acked-by: Fugang Duan Signed-off-by: Peter Chen --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 5079ca6ce1d1..5e76223e4570 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -302,6 +302,8 @@ patternProperties: description: Cirrus Logic, Inc. "^cisco,.*": description: Cisco Systems, Inc. + "^cix,.*": + description: CIX Technology Group Co., Ltd. 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2025 06:24:21.6229 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c18eac63-fda1-4712-4ddd-08dd6a9c8403 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: HK3PEPF0000021D.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6191 Content-Type: text/plain; charset="utf-8" Add device tree bindings for CIX P1 (Internal name sky1) Arm SoC, it consists several SoC models like CP8180, CD8180, etc. Reviewed-by: Krzysztof Kozlowski Acked-by: Fugang Duan Signed-off-by: Peter Chen --- .../devicetree/bindings/arm/cix.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cix.yaml diff --git a/Documentation/devicetree/bindings/arm/cix.yaml b/Documentation= /devicetree/bindings/arm/cix.yaml new file mode 100644 index 000000000000..114dab4bc4d2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cix.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX platforms + +maintainers: + - Peter Chen + - Fugang Duan + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Radxa Orion O6 + items: + - const: radxa,orion-o6 + - const: cix,sky1 + +additionalProperties: true + +... --=20 2.25.1 From nobody Fri Dec 19 04:02:20 2025 Received: from APC01-SG2-obe.outbound.protection.outlook.com (mail-sg2apc01on2096.outbound.protection.outlook.com [40.107.215.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26CDA18DB34; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2025 06:24:21.7094 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1aedce0f-0361-47a5-1c1e-08dd6a9c840e X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: HK3PEPF0000021F.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB6612 Content-Type: text/plain; charset="utf-8" From: Fugang Duan Add ARCH_CIX for CIX SoC series support. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Fugang Duan Signed-off-by: Peter Chen --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 02f9248f7c84..abe41db9b9b3 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -106,6 +106,12 @@ config ARCH_BLAIZE help This enables support for the Blaize SoC family =20 +config ARCH_CIX + bool "Cixtech SoC family" + help + This enables support for the Cixtech SoC family, + like P1(sky1). + config ARCH_EXYNOS bool "Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG --=20 2.25.1 From nobody Fri Dec 19 04:02:20 2025 Received: from APC01-TYZ-obe.outbound.protection.outlook.com (mail-tyzapc01on2102.outbound.protection.outlook.com [40.107.117.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14DB333981; Mon, 24 Mar 2025 06:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2025 06:24:21.8705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a93fd03-11b6-4562-7669-08dd6a9c842b X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: HK3PEPF00000221.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6575 Content-Type: text/plain; charset="utf-8" Enable CIX SoC support at ARM64 defconfig Reviewed-by: Krzysztof Kozlowski Acked-by: Fugang Duan Signed-off-by: Peter Chen --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index cb7da4415599..1dd46d200401 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -45,6 +45,7 @@ CONFIG_ARCH_BCMBCA=3Dy CONFIG_ARCH_BRCMSTB=3Dy CONFIG_ARCH_BERLIN=3Dy CONFIG_ARCH_BLAIZE=3Dy +CONFIG_ARCH_CIX=3Dy CONFIG_ARCH_EXYNOS=3Dy CONFIG_ARCH_SPARX5=3Dy CONFIG_ARCH_K3=3Dy --=20 2.25.1 From nobody Fri Dec 19 04:02:20 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023141.outbound.protection.outlook.com [40.107.44.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5F3D18DB20; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2025 06:24:23.7250 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d0856db-b715-453e-ab13-08dd6a9c8541 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: HK3PEPF0000021F.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR0601MB5862 Content-Type: text/plain; charset="utf-8" CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech, and Orion O6 is open source motherboard launched by Radxa. See below for detail: https://docs.radxa.com/en/orion/o6/getting-started/introduction In this commit, it only adds limited components for running initramfs at Orion O6. Reviewed-by: Krzysztof Kozlowski Acked-by: Fugang Duan Signed-off-by: Peter Chen --- Changes for v5: - Delete pmu-spe node which need to refine, and add it in future Changes for v4: - Add ppi-partition entry for gic-v3 node, and let pmu-a520 and pmu-a720's = interrupt entry get its handle - Remove gic-v3's #redistributor-regions and redistributor-stride properties - Change gic-v3's #interrupt-cells as 4, and change all interrupt specifier= s accordingly - Remove "arm,no-tick-in-suspend" for timer due to global counter is at alw= ays-on power domain - Remove timer's clock frequency due to firmware has already set it - Add Krzysztof Kozlowski's reviewed-by Changes for v3: - Fix two dts coding sytle issues=20 Changes for v2: - Corrects the SoF tag's name - Fix several coding sytle issues - move linux,cma node to dts file - delete memory node, memory size is passed by firmware - delete uart2 node which will be added in future patches - Improve for pmu and cpu node to stands for more specific cpu model - Improve the timer node and add hypervisor virtual timer irq - Pass "make O=3D$OUTKNL CHECK_DTBS=3Dy W=3D1 cix/sky1-orion-o6.dtb" arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/cix/Makefile | 2 + arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 26 +++ arch/arm64/boot/dts/cix/sky1.dtsi | 217 ++++++++++++++++++++++ 4 files changed, 246 insertions(+) create mode 100644 arch/arm64/boot/dts/cix/Makefile create mode 100644 arch/arm64/boot/dts/cix/sky1-orion-o6.dts create mode 100644 arch/arm64/boot/dts/cix/sky1.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..8e7ccd0027bd 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -13,6 +13,7 @@ subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom subdir-y +=3D cavium +subdir-y +=3D cix subdir-y +=3D exynos subdir-y +=3D freescale subdir-y +=3D hisilicon diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Mak= efile new file mode 100644 index 000000000000..ed3713982012 --- /dev/null +++ b/arch/arm64/boot/dts/cix/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_CIX) +=3D sky1-orion-o6.dtb diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts new file mode 100644 index 000000000000..78f4fcd87216 --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +/dts-v1/; + +#include "sky1.dtsi" +/ { + model =3D "Radxa Orion O6"; + compatible =3D "radxa,orion-o6", "cix,sky1"; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x0 0x28000000>; + linux,cma-default; + }; + }; +}; diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi new file mode 100644 index 000000000000..5bfeeea454e0 --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x200>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a520"; + enable-method =3D "psci"; + reg =3D <0x0 0x300>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <403>; + }; + + cpu4: cpu@400 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x400>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu5: cpu@500 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x500>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu6: cpu@600 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x600>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu7: cpu@700 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x700>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu8: cpu@800 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x800>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu9: cpu@900 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0x900>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu10: cpu@a00 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0xa00>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu11: cpu@b00 { + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + reg =3D <0x0 0xb00>; + device_type =3D "cpu"; + capacity-dmips-mhz =3D <1024>; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + core4 { + cpu =3D <&cpu4>; + }; + core5 { + cpu =3D <&cpu5>; + }; + core6 { + cpu =3D <&cpu6>; + }; + core7 { + cpu =3D <&cpu7>; + }; + core8 { + cpu =3D <&cpu8>; + }; + core9 { + cpu =3D <&cpu9>; + }; + core10 { + cpu =3D <&cpu10>; + }; + core11 { + cpu =3D <&cpu11>; + }; + }; + }; + }; + + pmu-a520 { + compatible =3D "arm,cortex-a520-pmu"; + interrupts =3D ; + }; + + pmu-a720 { + compatible =3D "arm,cortex-a720-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + soc@0 { + compatible =3D "simple-bus"; + ranges =3D <0 0 0 0 0x20 0>; + dma-ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + gic: interrupt-controller@e010000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x0e010000 0 0x10000>, /* GICD */ + <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ + interrupts =3D ; + #interrupt-cells =3D <4>; + interrupt-controller; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@e050000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x0e050000 0x0 0x30000>; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2025 06:24:23.6348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db6cf92a-ed8b-42fa-2241-08dd6a9c852f X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E6.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6282 Content-Type: text/plain; charset="utf-8" Using this entry as the maintainers information for CIX SoCs. Acked-by: Fugang Duan Signed-off-by: Peter Chen --- Changes for v5: - Refine MAINTAINERS for all CIX SoC - Add T for code tree location - Add K for Content regex Changes for v4: - Add two dts files as maintained files MAINTAINERS | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index efee40ea589f..f400e2de573b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2354,6 +2354,17 @@ F: arch/arm/boot/compressed/misc-ep93xx.h F: arch/arm/mach-ep93xx/ F: drivers/iio/adc/ep93xx_adc.c =20 +ARM/CIX SOC SUPPORT +M: Peter Chen +M: Fugang Duan +R: CIX Linux Kernel Upstream Group +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git +F: Documentation/devicetree/bindings/arm/cix.yaml +F: arch/arm64/boot/dts/cix/ +K: \bcix\b + ARM/CLKDEV SUPPORT M: Russell King L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.25.1