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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ebcd0dfb33sm5715937a12.68.2025.03.24.01.41.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Mar 2025 01:41:08 -0700 (PDT) From: Luca Weiss Date: Mon, 24 Mar 2025 09:41:03 +0100 Subject: [PATCH v2 3/4] clk: qcom: Add video clock controller driver for SM6350 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250324-sm6350-videocc-v2-3-cc22386433f4@fairphone.com> References: <20250324-sm6350-videocc-v2-0-cc22386433f4@fairphone.com> In-Reply-To: <20250324-sm6350-videocc-v2-0-cc22386433f4@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.14.2 From: Konrad Dybcio Add support for the video clock controller found on SM6350 based devices. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Co-developed-by: Luca Weiss Signed-off-by: Luca Weiss --- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-sm6350.c | 355 ++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 365 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 7d5dac26b244bfe785370033ad8ba49876d6627d..602e35d3d6c5b3b76947d892bb7= 05fe742daf081 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1329,6 +1329,15 @@ config SA_VIDEOCC_8775P Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config SM_VIDEOCC_6350 + tristate "SM6350 Video Clock Controller" + select SM_GCC_6350 + select QCOM_GDSC + help + Support for the video clock controller on SM6350 devices. + Say Y if you want to support video devices and functionality such as + video encode and decode. + config SM_VIDEOCC_7150 tristate "SM7150 Video Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 96862e99e5d432bbfba193c961d59ec5e601f10a..70895bc465549b87c7c7a8dc6f8= ac84c223a85d6 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -164,6 +164,7 @@ obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) +=3D tcsrcc-sm8650.o obj-$(CONFIG_SM_TCSRCC_8750) +=3D tcsrcc-sm8750.o +obj-$(CONFIG_SM_VIDEOCC_6350) +=3D videocc-sm6350.o obj-$(CONFIG_SM_VIDEOCC_7150) +=3D videocc-sm7150.o obj-$(CONFIG_SM_VIDEOCC_8150) +=3D videocc-sm8150.o obj-$(CONFIG_SM_VIDEOCC_8250) +=3D videocc-sm8250.o diff --git a/drivers/clk/qcom/videocc-sm6350.c b/drivers/clk/qcom/videocc-s= m6350.c new file mode 100644 index 0000000000000000000000000000000000000000..34bdc5aa865ac3e0c23ac1a2f5e= 471d3cfe64192 --- /dev/null +++ b/drivers/clk/qcom/videocc-sm6350.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, Konrad Dybcio + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" + +enum { + DT_IFACE, + DT_BI_TCXO, + DT_SLEEP_CLK, +}; + +enum { + P_BI_TCXO, + P_CHIP_SLEEP_CLK, + P_VIDEO_PLL0_OUT_EVEN, +}; + +static const struct pll_vco fabia_vco[] =3D { + { 125000000, 1000000000, 1 }, +}; + +/* 600 MHz */ +static const struct alpha_pll_config video_pll0_config =3D { + .l =3D 0x1f, + .alpha =3D 0x4000, + .config_ctl_val =3D 0x20485699, + .config_ctl_hi_val =3D 0x00002067, + .test_ctl_val =3D 0x40000000, + .test_ctl_hi_val =3D 0x00000002, + .user_ctl_val =3D 0x00000101, + .user_ctl_hi_val =3D 0x00004005, +}; + +static struct clk_alpha_pll video_pll0 =3D { + .offset =3D 0x0, + .vco_table =3D fabia_vco, + .num_vco =3D ARRAY_SIZE(fabia_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_video_pll0_out_even[] =3D= { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv video_pll0_out_even =3D { + .offset =3D 0x0, + .post_div_shift =3D 8, + .post_div_table =3D post_div_table_video_pll0_out_even, + .num_post_div =3D ARRAY_SIZE(post_div_table_video_pll0_out_even), + .width =3D 4, + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_pll0_out_even", + .parent_hws =3D (const struct clk_hw*[]) { + &video_pll0.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_PLL0_OUT_EVEN, 3 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_pll0_out_even.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_CHIP_SLEEP_CLK, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_SLEEP_CLK }, +}; + +static const struct freq_tbl ftbl_video_cc_iris_clk_src[] =3D { + F(133250000, P_VIDEO_PLL0_OUT_EVEN, 2, 0, 0), + F(240000000, P_VIDEO_PLL0_OUT_EVEN, 1.5, 0, 0), + F(300000000, P_VIDEO_PLL0_OUT_EVEN, 1, 0, 0), + F(380000000, P_VIDEO_PLL0_OUT_EVEN, 1, 0, 0), + F(460000000, P_VIDEO_PLL0_OUT_EVEN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_iris_clk_src =3D { + .cmd_rcgr =3D 0x1000, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_iris_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_iris_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] =3D { + F(32764, P_CHIP_SLEEP_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_sleep_clk_src =3D { + .cmd_rcgr =3D 0x701c, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_sleep_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch video_cc_iris_ahb_clk =3D { + .halt_reg =3D 0x5004, + .halt_check =3D BRANCH_VOTED, + .clkr =3D { + .enable_reg =3D 0x5004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_iris_ahb_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_iris_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_axi_clk =3D { + .halt_reg =3D 0x800c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x800c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_core_clk =3D { + .halt_reg =3D 0x3010, + .halt_check =3D BRANCH_VOTED, + .hwcg_reg =3D 0x3010, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x3010, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_iris_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvsc_core_clk =3D { + .halt_reg =3D 0x2014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x2014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvsc_core_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_iris_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvsc_ctl_axi_clk =3D { + .halt_reg =3D 0x8004, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8004, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvsc_ctl_axi_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_sleep_clk =3D { + .halt_reg =3D 0x7034, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x7034, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_sleep_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_sleep_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ahb_clk =3D { + .halt_reg =3D 0x801c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x801c, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_venus_ahb_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mvsc_gdsc =3D { + .gdscr =3D 0x2004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "mvsc_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, +}; + +static struct gdsc mvs0_gdsc =3D { + .gdscr =3D 0x3004, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "mvs0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER, +}; + +static struct gdsc *video_cc_sm6350_gdscs[] =3D { + [MVSC_GDSC] =3D &mvsc_gdsc, + [MVS0_GDSC] =3D &mvs0_gdsc, +}; + +static struct clk_regmap *video_cc_sm6350_clocks[] =3D { + [VIDEO_CC_IRIS_AHB_CLK] =3D &video_cc_iris_ahb_clk.clkr, + [VIDEO_CC_IRIS_CLK_SRC] =3D &video_cc_iris_clk_src.clkr, + [VIDEO_CC_MVS0_AXI_CLK] =3D &video_cc_mvs0_axi_clk.clkr, + [VIDEO_CC_MVS0_CORE_CLK] =3D &video_cc_mvs0_core_clk.clkr, + [VIDEO_CC_MVSC_CORE_CLK] =3D &video_cc_mvsc_core_clk.clkr, + [VIDEO_CC_MVSC_CTL_AXI_CLK] =3D &video_cc_mvsc_ctl_axi_clk.clkr, + [VIDEO_CC_SLEEP_CLK] =3D &video_cc_sleep_clk.clkr, + [VIDEO_CC_SLEEP_CLK_SRC] =3D &video_cc_sleep_clk_src.clkr, + [VIDEO_CC_VENUS_AHB_CLK] =3D &video_cc_venus_ahb_clk.clkr, + [VIDEO_PLL0] =3D &video_pll0.clkr, + [VIDEO_PLL0_OUT_EVEN] =3D &video_pll0_out_even.clkr, +}; + +static const struct regmap_config video_cc_sm6350_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xb000, + .fast_io =3D true, +}; + +static const struct qcom_cc_desc video_cc_sm6350_desc =3D { + .config =3D &video_cc_sm6350_regmap_config, + .clks =3D video_cc_sm6350_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_sm6350_clocks), + .gdscs =3D video_cc_sm6350_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_sm6350_gdscs), +}; + +static const struct of_device_id video_cc_sm6350_match_table[] =3D { + { .compatible =3D "qcom,sm6350-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_sm6350_match_table); + +static int video_cc_sm6350_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap =3D qcom_cc_map(pdev, &video_cc_sm6350_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config); + + /* Keep some clocks always-on */ + qcom_branch_set_clk_en(regmap, 0x7018); /* VIDEO_CC_XO_CLK */ + + return qcom_cc_really_probe(&pdev->dev, &video_cc_sm6350_desc, regmap); +} + +static struct platform_driver video_cc_sm6350_driver =3D { + .probe =3D video_cc_sm6350_probe, + .driver =3D { + .name =3D "video_cc-sm6350", + .of_match_table =3D video_cc_sm6350_match_table, + }, +}; + +module_platform_driver(video_cc_sm6350_driver); + +MODULE_DESCRIPTION("QTI VIDEO_CC SM6350 Driver"); +MODULE_LICENSE("GPL"); --=20 2.49.0