From nobody Thu Dec 18 23:25:22 2025 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 180601C84D5 for ; Sat, 22 Mar 2025 06:34:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742625292; cv=none; b=JkcuyRc8UHzuchWOjz4gCxGwpoex/CodrG8Otd0fQCaAoJQ88f7ATlPZAYTnXit4cRw0WTrNwoSrfMYv0IszER+EmF+t3jl3WndWOgixx6s/sYCDhe/lwfv3Q6b8Dl6fwNA9Kobc8fTzZ4uIwB9gVur7gmrMdVspqlqwsGb63KY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742625292; c=relaxed/simple; bh=p7Mb6vIPPHoTDt3eSFoj41xhRJUybxfZh++R1hxEinA=; h=Date:In-Reply-To:Message-Id:Mime-Version:References:Subject:From: To:Content-Type; b=Armbw9SjtIMD+WdEl0lsLkwfJGU/1ewKxdp+62OI3LL1ZnD8zhbP03VlHCwbir5oBApAFErFO1LUD5t7jSBXCbO8Ir0Hx1PsiUrhR682ZZX1KQAI2rU3/M+Nu4dU/BU8tIaZvuzOy5Gxyczy1xIg0ftcOjH/eHbSe3OW9bdPKhk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=Vle9+LlS; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Vle9+LlS" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-e54d9b54500so3795291276.3 for ; Fri, 21 Mar 2025 23:34:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1742625288; x=1743230088; darn=vger.kernel.org; h=content-transfer-encoding:to:from:subject:references:mime-version :message-id:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=0YeSs3HV21hPqxME9Y/uPxwXurItuHzesMa147bUg4c=; b=Vle9+LlSeDD/MqIbzwrtDQ3pNNjiqy3RGekqyraaX9Po6N0/XkCb7mTkBW/d2a2C5A /I4YhHqLpNVEHcTNnB7MiExNtH0iP6l9OVcCFqAy1WJ3CRt5VzGmE+0K3Xl0QUr+y+tS WLJ3hO6TuMITR8cK5nRjeDe9NTS5Kn4EMVXA0ZgDMOrvaN0OkLHr35llx4CaPedfQhZP 0P3KK/mtM+LTD4hcPziWo35+YXnEVRTXQfkLIE4vmigovHl7W2tqBRcg0pvBi4XoHhnR n+JpahncpkiCpm9P0a+Xh7XJDOpdwGXm8lxmEPLzrXjo7azWtFHGUjExvBXl2eWxwmRY HHUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742625288; x=1743230088; h=content-transfer-encoding:to:from:subject:references:mime-version :message-id:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=0YeSs3HV21hPqxME9Y/uPxwXurItuHzesMa147bUg4c=; b=ODete2+AoNHP3Yq1Oz5WPorbK6w4UxqpXhA3WOK4j1nXXsva/DzvJv+ebpR6tXc07R 8+6wPovP0d5G3qiZYVuD+V/B2yaQ1rPXr5jauxOVgBazIJ2ahDo8O5t2+Vi3h6qUHEsq 1VJLkw95OllS1bosBcLjmxx5+WdjHOZ9AUmwtfgLOhP6zA53ROzd4Zmgek9K+HUzVeFV /J06YcgVnd4XpQGlmGaUP3M5WwsvV32I/lpQ6K+WXAS/7WhNLgl5npi7NF58Tqvf08KU 9dpwBysYMVPvxeKqUZaW5Y5Knr4SkNlPG9sz0dlQWFHREP9AxB388aNJdtUibJURhVKA AYWw== X-Forwarded-Encrypted: i=1; AJvYcCWyFo8+O98GK+M4r6ihLrzNnBebfBUvfp2ODTuopVVhlmVrbyBdFUGOQ1hL8aE+2WZJ0jApVY49rUS0zQk=@vger.kernel.org X-Gm-Message-State: AOJu0YyNLRar6V258sE+Wb1JLBfmuFYzQkJweJ5duxY/JwX6Bh2DMOIJ Oca9qmj79Jv3RBiCfA+TZYLPv1BP3VZNTc35oyo4MaKW30Vi3x8SpmvxIS6idcT7/f2bP3SxcCv ub+zxpg== X-Google-Smtp-Source: AGHT+IFkFFjPxOXC/7mpxpt7UBovKLcy3XGxqctyZSKkAxXUCbhexPCz0PReL+b27LQOefJIYNeXSqnXEHuJ X-Received: from irogers.svl.corp.google.com ([2620:15c:2c5:11:c16d:a1c1:1823:1d0e]) (user=irogers job=sendgmr) by 2002:a25:aac2:0:b0:e63:6b57:2414 with SMTP id 3f1490d57ef6-e66a4d34ff3mr23600276.1.1742625287935; Fri, 21 Mar 2025 23:34:47 -0700 (PDT) Date: Fri, 21 Mar 2025 23:33:38 -0700 In-Reply-To: <20250322063403.364981-1-irogers@google.com> Message-Id: <20250322063403.364981-11-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250322063403.364981-1-irogers@google.com> X-Mailer: git-send-email 2.49.0.395.g12beb8f557-goog Subject: [PATCH v1 10/35] perf vendor events: Update elkhartlake events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , "=?UTF-8?q?Andreas=20F=C3=A4rber?=" , Manivannan Sadhasivam , Maxime Coquelin , Alexandre Torgue , Caleb Biggers , Weilin Wang , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Perry Taylor , Thomas Falcon Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update event topic moving other topic events to cache and memory. Signed-off-by: Ian Rogers --- .../arch/x86/elkhartlake/cache.json | 192 +++++++++ .../arch/x86/elkhartlake/memory.json | 202 +++++++++ .../arch/x86/elkhartlake/other.json | 394 ------------------ 3 files changed, 394 insertions(+), 394 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json b/tools/= perf/pmu-events/arch/x86/elkhartlake/cache.json index 7882dca9d5e1..1bb42acf1d48 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json @@ -357,6 +357,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3000000010000", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -367,6 +377,26 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8003000000000000", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -427,6 +457,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -487,6 +527,27 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", "Counter": "0,1,2,3", @@ -553,6 +614,27 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", "Counter": "0,1,2,3", @@ -613,6 +695,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -623,6 +715,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that have any type of resp= onse.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that were supplied by the = L3 cache where a snoop was sent, the snoop hit, and modified data was forwa= rded.", "Counter": "0,1,2,3", @@ -633,6 +735,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10040", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -693,6 +805,26 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000040", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10010", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -753,6 +885,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10020", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -813,6 +955,26 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000020", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010000", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -823,6 +985,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000000010000", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -843,6 +1015,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10477", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -903,6 +1085,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000477", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts streaming stores that were supplied by= the L3 cache.", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json b/tools= /perf/pmu-events/arch/x86/elkhartlake/memory.json index 34306ec24e9b..260a488540bb 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json @@ -25,6 +25,16 @@ "SampleAfterValue": "200003", "UMask": "0x4" }, + { + "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", "Counter": "0,1,2,3", @@ -45,6 +55,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -65,6 +85,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -85,6 +115,26 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -105,6 +155,27 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", "Counter": "0,1,2,3", @@ -127,6 +198,27 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "Counter": "0,1,2,3", + "Deprecated": "1", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", "Counter": "0,1,2,3", @@ -147,6 +239,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -167,6 +269,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -187,6 +299,26 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -207,6 +339,26 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -227,6 +379,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -317,6 +479,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", "Counter": "0,1,2,3", @@ -337,6 +509,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", "Counter": "0,1,2,3", @@ -357,6 +539,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", "Counter": "0,1,2,3", @@ -377,6 +569,16 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/= perf/pmu-events/arch/x86/elkhartlake/other.json index 57613207f7ad..35cdbfa617e7 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json @@ -116,26 +116,6 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts all code reads that were supplied by D= RAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000044", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all code reads that were supplied by D= RAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000044", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts all code reads that have an outstandin= g request. Returns the number of cycles until the response is received (i.e= . XQ to XQ latency).", "Counter": "0,1,2,3", @@ -146,180 +126,6 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.COREWB_M.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3000000010000", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.COREWB_M.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8003000000000000", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10004", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000004", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000004", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", - "Counter": "0,1,2,3", - "Deprecated": "1", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000001", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10002", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000002", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000002", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.DEMAND_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000002", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", "Counter": "0,1,2,3", @@ -330,146 +136,6 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that have any type of resp= onse.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10400", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10040", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000040", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000040", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000040", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10010", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000010", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000010", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10020", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000020", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000020", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000020", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.L1WB_M.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000000010000", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.L2WB_M.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000000010000", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that have any type of response.", "Counter": "0,1,2,3", @@ -500,46 +166,6 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10477", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000477", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x184000477", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.READS_TO_CORE.OUTSTANDING", - "MSRIndex": "0x1a6", - "MSRValue": "0x8000000000000477", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts streaming stores that have any type of= response.", "Counter": "0,1,2,3", @@ -560,26 +186,6 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x100184000000", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", - "Counter": "0,1,2,3", - "EventCode": "0XB7", - "EventName": "OCR.UC_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x100184000000", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts uncached memory reads that have an out= standing request. Returns the number of cycles until the response is receiv= ed (i.e. XQ to XQ latency).", "Counter": "0,1,2,3", --=20 2.49.0.395.g12beb8f557-goog