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Update the qcom,pcie-common.yaml to include the phy, phy-names, and wake-gpios properties in the root port node. There is already reset-gpio defined for PERST# in pci-bus-common.yaml, start using that property instead of perst-gpio. For backward compatibility, do not remove any existing properties in the bridge node. [1] https://lore.kernel.org/linux-pci/20241211192014.GA3302752@bhelgaas/ Signed-off-by: Krishna Chaitanya Chundru --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 22 ++++++++++++++++++= ++++ .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 18 ++++++++++++++---- 2 files changed, 36 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0480c58f7d99..258c21c01c72 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -85,6 +85,28 @@ properties: opp-table: type: object =20 +patternProperties: + "^pcie@": + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + + unevaluatedProperties: false + required: - reg - reg-names diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 76cb9fbfd476..c0a7cfdbfd2a 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -162,9 +162,6 @@ examples: iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; =20 - phys =3D <&pcie1_phy>; - phy-names =3D "pciephy"; - pinctrl-names =3D "default"; pinctrl-0 =3D <&pcie1_clkreq_n>; =20 @@ -173,7 +170,20 @@ examples: resets =3D <&gcc GCC_PCIE_1_BCR>; reset-names =3D "pci"; =20 - perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply =3D <&pp3300_ssd>; + pcieport1: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + phys =3D <&pcie1_phy>; + phy-names =3D "pciephy"; + + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + }; + }; }; --=20 2.34.1