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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f2cbdd0a21sm475553173.41.2025.03.21.08.18.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 08:18:42 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 6/7] clk: spacemit: define new syscons with only resets Date: Fri, 21 Mar 2025 10:18:29 -0500 Message-ID: <20250321151831.623575-7-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321151831.623575-1-elder@riscstar.com> References: <20250321151831.623575-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable support for three additional syscon CCUs which support reset controls but no clocks: ARCPU, RCPU2, and APBC2. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 106 ++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 17e321c25959a..bf5a3e2048619 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,6 +130,37 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec =20 +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +/* XXX Next one is part of the AUD_AUDCLOCK region @ 0xc0882000 */ +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + struct spacemit_ccu_clk { int id; struct clk_hw *hw; @@ -1781,6 +1812,69 @@ static const struct k1_ccu_data k1_ccu_apmu_data =3D= { .rst_data =3D &apmu_reset_controller_data, }; =20 +static const struct ccu_reset_data rcpu_reset_data[] =3D { + [RST_RCPU_SSP0] =3D RST_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), + [RST_RCPU_I2C0] =3D RST_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), + [RST_RCPU_UART1] =3D RST_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), + [RST_RCPU_IR] =3D RST_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), + [RST_RCPU_CAN] =3D RST_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), + [RST_RCPU_UART0] =3D RST_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), + [RST_RCPU_HDMI_AUDIO] =3D RST_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data rcpu_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(rcpu_reset_data), + .data =3D rcpu_reset_data, +}; + +static struct k1_ccu_data k1_ccu_rcpu_data =3D { + /* No clocks in the RCPU CCU */ + .rst_data =3D &rcpu_reset_controller_data, +}; + +static const struct ccu_reset_data rcpu2_reset_data[] =3D { + [RST_RCPU2_PWM0] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM1] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM2] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM3] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM4] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM5] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM6] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM7] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM8] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_RCPU2_PWM9] =3D RST_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), +}; + +static const struct ccu_reset_controller_data rcpu2_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(rcpu2_reset_data), + .data =3D rcpu2_reset_data, +}; + +static struct k1_ccu_data k1_ccu_rcpu2_data =3D { + /* No clocks in the RCPU2 CCU */ + .rst_data =3D &rcpu2_reset_controller_data, +}; + +static const struct ccu_reset_data apbc2_reset_data[] =3D { + [RST_APBC2_UART1] =3D RST_DATA(APBC2_UART1_CLK_RST, BIT(2), (0)), + [RST_APBC2_SSP2] =3D RST_DATA(APBC2_SSP2_CLK_RST, BIT(2), (0)), + [RST_APBC2_TWSI3] =3D RST_DATA(APBC2_TWSI3_CLK_RST, BIT(2), (0)), + [RST_APBC2_RTC] =3D RST_DATA(APBC2_RTC_CLK_RST, BIT(2), (0)), + [RST_APBC2_TIMERS0] =3D RST_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), (0)), + [RST_APBC2_KPC] =3D RST_DATA(APBC2_KPC_CLK_RST, BIT(2), (0)), + [RST_APBC2_GPIO] =3D RST_DATA(APBC2_GPIO_CLK_RST, BIT(2), (0)), +}; + +static const struct ccu_reset_controller_data apbc2_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(apbc2_reset_data), + .data =3D apbc2_reset_data, +}; + +static struct k1_ccu_data k1_ccu_apbc2_data =3D { + /* No clocks in the RCPU2 CCU */ + .rst_data =3D &apbc2_reset_controller_data, +}; + static struct ccu_reset_controller * rcdev_to_controller(struct reset_controller_dev *rcdev) { @@ -1959,6 +2053,18 @@ static const struct of_device_id of_k1_ccu_match[] = =3D { .compatible =3D "spacemit,k1-syscon-apmu", .data =3D &k1_ccu_apmu_data, }, + { + .compatible =3D "spacemit,k1-syscon-rcpu", + .data =3D &k1_ccu_rcpu_data, + }, + { + .compatible =3D "spacemit,k1-syscon-rcpu2", + .data =3D &k1_ccu_rcpu2_data, + }, + { + .compatible =3D "spacemit,k1-syscon-apbc2", + .data =3D &k1_ccu_apbc2_data, + }, { } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match); --=20 2.43.0