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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f2cbdd0a21sm475553173.41.2025.03.21.08.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 08:18:40 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RESEND 4/7] clk: spacemit: define existing syscon resets Date: Fri, 21 Mar 2025 10:18:27 -0500 Message-ID: <20250321151831.623575-5-elder@riscstar.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321151831.623575-1-elder@riscstar.com> References: <20250321151831.623575-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define reset controls associated with the MPMU, APBC, and APMU SpacemiT K1 CCUs. These already have clocks associated with them. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 132 ++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 6d879411c6c05..be8abd27753cb 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -151,6 +151,13 @@ struct k1_ccu_data { const struct ccu_reset_controller_data *rst_data; }; =20 +#define RST_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset =3D (_offset), \ + .assert_mask =3D (_assert_mask), \ + .deassert_mask =3D (_deassert_mask), \ + } + struct ccu_reset_controller { struct regmap *regmap; const struct ccu_reset_controller_data *data; @@ -1428,6 +1435,7 @@ static struct spacemit_ccu_clk k1_ccu_apbs_clks[] =3D= { =20 static const struct k1_ccu_data k1_ccu_apbs_data =3D { .clk =3D k1_ccu_apbs_clks, + /* No resets in the APBS CCU */ }; =20 static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] =3D { @@ -1467,8 +1475,18 @@ static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = =3D { { 0, NULL }, }; =20 +static const struct ccu_reset_data mpmu_reset_data[] =3D { + [RST_WDT] =3D RST_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data mpmu_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(mpmu_reset_data), + .data =3D mpmu_reset_data, +}; + static const struct k1_ccu_data k1_ccu_mpmu_data =3D { .clk =3D k1_ccu_mpmu_clks, + .rst_data =3D &mpmu_reset_controller_data, }; =20 static struct spacemit_ccu_clk k1_ccu_apbc_clks[] =3D { @@ -1575,8 +1593,68 @@ static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = =3D { { 0, NULL }, }; =20 +static const struct ccu_reset_data apbc_reset_data[] =3D { + [RST_UART0] =3D RST_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RST_UART2] =3D RST_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RST_GPIO] =3D RST_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RST_PWM0] =3D RST_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RST_PWM1] =3D RST_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RST_PWM2] =3D RST_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RST_PWM3] =3D RST_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RST_PWM4] =3D RST_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RST_PWM5] =3D RST_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RST_PWM6] =3D RST_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RST_PWM7] =3D RST_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RST_PWM8] =3D RST_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RST_PWM9] =3D RST_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RST_PWM10] =3D RST_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RST_PWM11] =3D RST_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RST_PWM12] =3D RST_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RST_PWM13] =3D RST_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RST_PWM14] =3D RST_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RST_PWM15] =3D RST_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RST_PWM16] =3D RST_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RST_PWM17] =3D RST_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RST_PWM18] =3D RST_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RST_PWM19] =3D RST_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RST_SSP3] =3D RST_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RST_UART3] =3D RST_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RST_RTC] =3D RST_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RST_TWSI0] =3D RST_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RST_TIMERS1] =3D RST_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RST_AIB] =3D RST_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RST_TIMERS2] =3D RST_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RST_ONEWIRE] =3D RST_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RST_SSPA0] =3D RST_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RST_SSPA1] =3D RST_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RST_DRO] =3D RST_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RST_IR] =3D RST_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RST_TWSI1] =3D RST_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RST_TSEN] =3D RST_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RST_TWSI2] =3D RST_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RST_TWSI4] =3D RST_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RST_TWSI5] =3D RST_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RST_TWSI6] =3D RST_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RST_TWSI7] =3D RST_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RST_TWSI8] =3D RST_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RST_IPC_AP2AUD] =3D RST_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RST_UART4] =3D RST_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RST_UART5] =3D RST_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RST_UART6] =3D RST_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RST_UART7] =3D RST_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RST_UART8] =3D RST_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RST_UART9] =3D RST_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RST_CAN0] =3D RST_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data apbc_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(apbc_reset_data), + .data =3D apbc_reset_data, +}; + static const struct k1_ccu_data k1_ccu_apbc_data =3D { .clk =3D k1_ccu_apbc_clks, + .rst_data =3D &apbc_reset_controller_data, }; =20 static struct spacemit_ccu_clk k1_ccu_apmu_clks[] =3D { @@ -1645,8 +1723,62 @@ static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = =3D { { 0, NULL }, }; =20 +static const struct ccu_reset_data apmu_reset_data[] =3D { + [RST_CCIC_4X] =3D RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RST_CCIC1_PHY] =3D RST_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RST_SDH_AXI] =3D RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RST_SDH0] =3D RST_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RST_SDH1] =3D RST_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RST_SDH2] =3D RST_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RST_USBP1_AXI] =3D RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RST_USB_AXI] =3D RST_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RST_USB3_0] =3D RST_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(9)|BIT(10)|BIT(11)), + [RST_QSPI] =3D RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RST_QSPI_BUS] =3D RST_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RST_DMA] =3D RST_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RST_AES] =3D RST_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RST_VPU] =3D RST_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RST_GPU] =3D RST_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RST_EMMC] =3D RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RST_EMMC_X] =3D RST_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RST_AUDIO] =3D RST_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(0) | BIT(2) | BIT(3)), + [RST_HDMI] =3D RST_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RST_PCIE0] =3D RST_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(3) | BIT(4) | BIT(5)), + [RST_PCIE1] =3D RST_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(3) | BIT(4) | BIT(5)), + [RST_PCIE2] =3D RST_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(3) | BIT(4) | BIT(5)), + [RST_EMAC0] =3D RST_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RST_EMAC1] =3D RST_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RST_JPG] =3D RST_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RST_CCIC2PHY] =3D RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RST_CCIC3PHY] =3D RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RST_CSI] =3D RST_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RST_ISP] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RST_ISP_CPP] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RST_ISP_BUS] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RST_ISP_CI] =3D RST_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RST_DPU_MCLK] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RST_DPU_ESC] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RST_DPU_HCLK] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RST_DPU_SPIBUS] =3D RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RST_DPU_SPI_HBUS] =3D RST_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RST_V2D] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RST_MIPI] =3D RST_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RST_MC] =3D RST_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data apmu_reset_controller_data = =3D { + .count =3D ARRAY_SIZE(apmu_reset_data), + .data =3D apmu_reset_data, +}; + static const struct k1_ccu_data k1_ccu_apmu_data =3D { .clk =3D k1_ccu_apmu_clks, + .rst_data =3D &apmu_reset_controller_data, }; =20 static struct ccu_reset_controller * --=20 2.43.0