From nobody Wed Dec 17 12:10:17 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 355A71F55FB; Fri, 21 Mar 2025 09:35:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742549738; cv=none; b=Ko4wahjZrCWM0R+RYIxr1vWml+FrUxb1XwVUXPbAgSqEbXADOPKLlUwkTx8Arms402vfsf72hKfTOtOSJzITsvPTd3E984bX5yBVe2nxwjFv4cejDcr05KaKxRttm+Y0qOPRVsFU1oAdO1OVbK51wVrG6txnZ9Phej6VIf3KRZE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742549738; c=relaxed/simple; bh=bo92NplUd9V3kn/n7SBrZIaaOgB6dUMB3PeAQpnvzpw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pyTktXnauh1uRT5q4Zb5vZMRn53T5eHwNmpFi/XnKWRL6glJpQeP1uHi0D9TlK/QhaVLT0N13NsX3oxEfdMV+Cd9LKwxuU6i2AYLKIxWILR3zbmpCXkKS7ZP6KoyBpUVJ6D3qEybh+rd3N5O115pYO40aK7evG4ZVo2pL27CfsI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=a6+mX4vG; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="a6+mX4vG" X-UUID: d5aac74c063711f0aae1fd9735fae912-20250321 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LLRkNEfiUwwBdAm647qFSGmIV09OH8rduF+W1MyPamo=; b=a6+mX4vGYRjjSUUpBTDxYb59dkucGavIiWpyO8H0N98LhBVDDhnJlzbWyQkEL4EaFlT3sqX5lZe/ABx6IkAPA1Q2V8PnBn+GPVMgujV2xqiKPH4rJ2U7XJvQELpwL3mNAVmpUrnBg2BUyMOUeiNMn6IXPRIWSqDax7gLhYxGYtM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:00af1bac-285e-4f2d-a6fd-5ce989770838,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:e57aa1c6-16da-468a-87f7-8ca8d6b3b9f7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: d5aac74c063711f0aae1fd9735fae912-20250321 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 312089309; Fri, 21 Mar 2025 17:35:32 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N1.mediatek.inc (172.21.101.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 21 Mar 2025 17:35:31 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 21 Mar 2025 17:35:31 +0800 From: paul-pl.chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 07/15] soc: mediatek: mutex: refactor SOF settings for output components Date: Fri, 21 Mar 2025 17:33:36 +0800 Message-ID: <20250321093435.94835-8-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250321093435.94835-1-paul-pl.chen@mediatek.com> References: <20250321093435.94835-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nancy Lin Refactor SOF settings by adding mtk_mutex_get_output_comp_sof() and extracting SOF logic from mtk_mutex_add_comp() and mtk_mutex_remove_comp(). - Added mtk_mutex_add_comp_sof() and mtk_mutex_remove_comp_sof() for SOF settings. - Reused the switch case for SOF IDs. - Separated MOD and SOF logic. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- drivers/soc/mediatek/mtk-mutex.c | 121 +++++++++++++++---------- include/linux/soc/mediatek/mtk-mutex.h | 4 + 2 files changed, 79 insertions(+), 46 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index aaa965d4b050..c026ac0e6969 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -853,43 +853,84 @@ void mtk_mutex_unprepare(struct mtk_mutex *mutex) } EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); =20 -void mtk_mutex_add_comp(struct mtk_mutex *mutex, - enum mtk_ddp_comp_id id) +static int mtk_mutex_get_output_comp_sof(enum mtk_ddp_comp_id id) { - struct mtk_mutex_ctx *mtx =3D container_of(mutex, struct mtk_mutex_ctx, - mutex[mutex->id]); - unsigned int reg; - unsigned int sof_id; - unsigned int offset; - - WARN_ON(&mtx->mutex[mutex->id] !=3D mutex); - switch (id) { case DDP_COMPONENT_DSI0: - sof_id =3D MUTEX_SOF_DSI0; - break; + return MUTEX_SOF_DSI0; case DDP_COMPONENT_DSI1: - sof_id =3D MUTEX_SOF_DSI0; - break; + return MUTEX_SOF_DSI1; case DDP_COMPONENT_DSI2: - sof_id =3D MUTEX_SOF_DSI2; - break; + return MUTEX_SOF_DSI2; case DDP_COMPONENT_DSI3: - sof_id =3D MUTEX_SOF_DSI3; - break; + return MUTEX_SOF_DSI3; case DDP_COMPONENT_DPI0: - sof_id =3D MUTEX_SOF_DPI0; - break; + return MUTEX_SOF_DPI0; case DDP_COMPONENT_DPI1: - sof_id =3D MUTEX_SOF_DPI1; - break; + return MUTEX_SOF_DPI1; case DDP_COMPONENT_DP_INTF0: - sof_id =3D MUTEX_SOF_DP_INTF0; - break; + return MUTEX_SOF_DP_INTF0; case DDP_COMPONENT_DP_INTF1: - sof_id =3D MUTEX_SOF_DP_INTF1; - break; + return MUTEX_SOF_DP_INTF1; default: + break; + } + + return -EINVAL; +} + +void mtk_mutex_add_comp_sof(struct mtk_mutex *mutex, enum mtk_ddp_comp_id = id) +{ + struct mtk_mutex_ctx *mtx =3D container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + int sof_id =3D mtk_mutex_get_output_comp_sof(id); + unsigned int offset; + + if (sof_id < 0 || sof_id >=3D DDP_MUTEX_SOF_MAX) + return; + + WARN_ON(&mtx->mutex[mutex->id] !=3D mutex); + + offset =3D DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id); + + writel_relaxed(mtx->data->mutex_sof[sof_id], + mtx->regs + offset); +} +EXPORT_SYMBOL_GPL(mtk_mutex_add_comp_sof); + +void mtk_mutex_remove_comp_sof(struct mtk_mutex *mutex, enum mtk_ddp_comp_= id id) +{ + struct mtk_mutex_ctx *mtx =3D container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + unsigned int reg; + int sof_id =3D mtk_mutex_get_output_comp_sof(id); + unsigned int offset; + + if (sof_id < 0 || sof_id >=3D DDP_MUTEX_SOF_MAX) + return; + + WARN_ON(&mtx->mutex[mutex->id] !=3D mutex); + + offset =3D DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id); + reg =3D readl_relaxed(mtx->regs + offset); + reg &=3D ~(1 << mtx->data->mutex_sof[id]); + + writel_relaxed(reg, mtx->regs + offset); +} +EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp_sof); + +void mtk_mutex_add_comp(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id) +{ + struct mtk_mutex_ctx *mtx =3D container_of(mutex, struct mtk_mutex_ctx, + mutex[mutex->id]); + unsigned int reg; + unsigned int offset; + bool is_output_comp =3D !!mtk_mutex_get_output_comp_sof(id); + + WARN_ON(&mtx->mutex[mutex->id] !=3D mutex); + + if (!is_output_comp) { if (mtx->data->mutex_mod[id] < 32) { offset =3D DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); @@ -902,12 +943,10 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, reg |=3D 1 << (mtx->data->mutex_mod[id] - 32); writel_relaxed(reg, mtx->regs + offset); } - return; } =20 - writel_relaxed(mtx->data->mutex_sof[sof_id], - mtx->regs + - DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id)); + if (is_output_comp) + mtk_mutex_add_comp_sof(mutex, id); } EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); =20 @@ -918,24 +957,11 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, mutex[mutex->id]); unsigned int reg; unsigned int offset; + bool is_output_comp =3D !!mtk_mutex_get_output_comp_sof(id); =20 WARN_ON(&mtx->mutex[mutex->id] !=3D mutex); =20 - switch (id) { - case DDP_COMPONENT_DSI0: - case DDP_COMPONENT_DSI1: - case DDP_COMPONENT_DSI2: - case DDP_COMPONENT_DSI3: - case DDP_COMPONENT_DPI0: - case DDP_COMPONENT_DPI1: - case DDP_COMPONENT_DP_INTF0: - case DDP_COMPONENT_DP_INTF1: - writel_relaxed(MUTEX_SOF_SINGLE_MODE, - mtx->regs + - DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, - mutex->id)); - break; - default: + if (!is_output_comp) { if (mtx->data->mutex_mod[id] < 32) { offset =3D DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id); @@ -948,8 +974,11 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, reg &=3D ~(1 << (mtx->data->mutex_mod[id] - 32)); writel_relaxed(reg, mtx->regs + offset); } - break; } + + if (is_output_comp) + mtk_mutex_remove_comp_sof(mutex, id); + } EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp); =20 diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/med= iatek/mtk-mutex.h index 635218e3ac68..515e2d8bfc90 100644 --- a/include/linux/soc/mediatek/mtk-mutex.h +++ b/include/linux/soc/mediatek/mtk-mutex.h @@ -69,6 +69,10 @@ enum mtk_mutex_sof_index { =20 struct mtk_mutex *mtk_mutex_get(struct device *dev); int mtk_mutex_prepare(struct mtk_mutex *mutex); +void mtk_mutex_add_comp_sof(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id); +void mtk_mutex_remove_comp_sof(struct mtk_mutex *mutex, + enum mtk_ddp_comp_id id); void mtk_mutex_add_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id); void mtk_mutex_enable(struct mtk_mutex *mutex); --=20 2.45.2