From nobody Wed Dec 17 12:10:12 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 901771F55FB; Fri, 21 Mar 2025 09:35:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742549732; cv=none; b=tVOzjE7bQ6s8LcNDLRSjl/7zutosjbrvMOaRVTpQ25WwjtCJbUucAeaPsASypT96BuNCkSjQI2pa34G1VQZPhULl1Op5muXJnJsmLPeZDLOlVxq/ohTeLJQijvI5SAdnlzj6VtasKFXqmDJZKIaf0rIstf2bN8Et0qhKRwHTsM0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742549732; c=relaxed/simple; bh=I0/SwEQ0S9i5WLebIcx1Ed7sV94+pUea+HIl5itZMA8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fOaiKn0RTDozr1et5JBo4TP2UT1I9L7Jw9kfSHArVT/9Cuq7VKBH5rtPEi8EwIzRZr3ug+f+fLORRyh2LMXQ8T0kLoQ9y/jV8EtrG1Kdy+UcdqNGBeNbPB8fBQdB5a8Bousx5IRVOV6E0+c41DUF5tc6v0A1w9SF5kaVL2muy9o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=MAVD6chp; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="MAVD6chp" X-UUID: d1554906063711f0aae1fd9735fae912-20250321 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=goXx0bw5S/4pcmZaDRo/lhBcOym7XT9NAEh4tbj1ZQs=; b=MAVD6chp+/g/ssU5XddmE2z2JosWSLI7KSdXZXSrNHDC9d9HR0WgUw3g5nBv7UI7mzKEx3+VNIJqgi9/tkSVMEpVbf/kNzTZpeb6qflcOh692SVsbS8Fhz+coKXaYxKU5SBj6g5sHCJi1FAAFKpAIhprWx9g5eVz9Vh3YKOUrzM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:4471265b-de74-4d11-aacf-094f4a0e307e,IP:0,UR L:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:6d12aa8c-f5b8-47d5-8cf3-b68fe7530c9a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|83|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OS A:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: d1554906063711f0aae1fd9735fae912-20250321 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1480242954; Fri, 21 Mar 2025 17:35:25 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 21 Mar 2025 17:35:23 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 21 Mar 2025 17:35:23 +0800 From: paul-pl.chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 05/15] dt-bindings: display: mediatek: add OUTPROC yaml for MT8196 Date: Fri, 21 Mar 2025 17:33:34 +0800 Message-ID: <20250321093435.94835-6-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250321093435.94835-1-paul-pl.chen@mediatek.com> References: <20250321093435.94835-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul-pl Chen Add mediate,outproc.yaml to support OUTPROC for MT8196. MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC,handles the post-stage of pixel processing in the overlapping procedure. Signed-off-by: Paul-pl Chen --- .../display/mediatek/mediatek,outproc.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,outproc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ou= tproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ou= tproc.yaml new file mode 100644 index 000000000000..f42e9abc1436 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,outproc.y= aml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,outproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display overlap output processor + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: | + MediaTek display overlap output processor, namely OVL_OUTPROC or OUTPROC, + handles the post-stage of pixel processing in the overlapping procedure. + OVL_OUTPROC manages pixels for gamma correction and ensures that pixel + values are within the correct range. + +properties: + compatible: + const: mediatek,mt8196-outproc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + disp_ovl0_outproc0: outproc@32970000 { + compatible =3D "mediatek,mt8196-outproc"; + reg =3D <0 0x32970000 0 0x1000>; + clocks =3D <&ovlsys_config_clk 49>; + interrupts =3D ; + }; + }; --=20 2.45.2