From nobody Wed Dec 17 13:57:54 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CABC1F12F4; Fri, 21 Mar 2025 09:35:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742549726; cv=none; b=FJD1oLuo8z2VtK6r+D0OT5ezaYQBPQWTLYEofARvKcc8LfQE3h2yjNYzogyR+6AL36NWRPwnp+X1/UFbFl7ErLIQLvNVuK0vbVVQM/Bp5X8cMcBZAHsGnZPxSxIXwPvOOC4xY0mtbFfk+ymtTEFoF4FQkS4Ay04HCIdjssX/XXA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742549726; c=relaxed/simple; bh=b1hnziLLwC1ziiXDMX3YT+Ifx/yoFPiPUjCaOgLdNf4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=EButMnd36FB8yr0VkxXYkdh6Qg1OM+8nvWXS/tTOlkfz8vRfsXeQyiMkMEbGIYXrmZoGj3QNnQpF4VUZFep5shbHzk9dRDxaBDaTjJbacx1V/aGA1JO29f2l5JPrxhlCVLNr3e84deqR7FDbito7EXG/jB3agsPxC9vG2diZ9OU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=qjKu+9ZW; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qjKu+9ZW" X-UUID: cc7c1266063711f08eb9c36241bbb6fb-20250321 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=dzn3KPVkY5CKPqLCw9mwkZHdcDl3t5MeFf7uK4V+q/U=; b=qjKu+9ZW6QPp+ek9B0L2WhP5XK/U11VkB2uBW2qpaiRxCFY4NX08Kj1+5r0GH6Ski/WIJNoAv3KinUNUuiSzNrj5KmGqmPA1WbeCUFhyBG9sSIZC/fl+Pxqlrr33gnPDXYr+VwV78sizgIAVvfUCuI9G8D04rPBliMndBT8fg2Q=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:8ebf1759-e52a-4bd5-920b-61271363162d,IP:0,UR L:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:307aa1c6-16da-468a-87f7-8ca8d6b3b9f7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:11|83|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OS A:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: cc7c1266063711f08eb9c36241bbb6fb-20250321 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1144991328; Fri, 21 Mar 2025 17:35:17 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 21 Mar 2025 17:35:15 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 21 Mar 2025 17:35:15 +0800 From: paul-pl.chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v2 03/15] dt-bindings: display: mediatek: add EXDMA yaml for MT8196 Date: Fri, 21 Mar 2025 17:33:32 +0800 Message-ID: <20250321093435.94835-4-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250321093435.94835-1-paul-pl.chen@mediatek.com> References: <20250321093435.94835-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul-pl Chen Add mediatek,exdma.yaml to support EXDMA for MT8196. The MediaTek display overlap extended DMA engine, namely OVL_EXDMA or EXDMA, primarily functions as a DMA engine for reading data from DRAM with various DRAM footprints and data formats. Signed-off-by: Paul-pl Chen --- .../bindings/dma/mediatek,exdma.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mediatek,exdma.ya= ml diff --git a/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml b/Do= cumentation/devicetree/bindings/dma/mediatek,exdma.yaml new file mode 100644 index 000000000000..de7f8283bb48 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mediatek,exdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display overlap extended DMA engine + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + The MediaTek display overlap extended DMA engine, namely OVL_EXDMA or EX= DMA, + primarily functions as a DMA engine for reading data from DRAM with vari= ous + DRAM footprints and data formats. For input sources in certain color for= mats + and color domains, OVL_EXDMA also includes a color transfer function + to process pixels into a consistent color domain. + +properties: + compatible: + const: mediatek,mt8196-exdma + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + mediatek,larb: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle to the local arbiters node in the current SoCs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. + + iommus: + maxItems: 1 + + '#dma-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - mediatek,larb + +additionalProperties: false + +examples: + - | + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + disp_ovl0_exdma2: dma-controller@32850000 { + compatible =3D "mediatek,mt8196-exdma"; + reg =3D <0 0x32850000 0 0x1000>; + clocks =3D <&ovlsys_config_clk 13>; + power-domains =3D <&hfrpsys 12>; + mediatek,larb =3D <&smi_larb0>; + iommus =3D <&mm_smmu 144>; + #dma-cells =3D <1>; + }; + }; --=20 2.45.2