From nobody Mon Feb 9 23:00:51 2026 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C2201EE7BC for ; Fri, 21 Mar 2025 07:38:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742542719; cv=none; b=dAB/d/JwQJlAwyBq6Y4dOJWKn55zCZOvttR+KIoO0aMRliquKdbOe5gD5RQjFSmltPhJqzKFYNXco5cJ0SIInpITh9fgVVV669GpEFRMl9uQ1ba87+9S8aL3Fdqvnl+GYM935xuwXlV1Ir9aU5VI6O/dh89mhp2XCtKIyji6TA4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742542719; c=relaxed/simple; bh=UWGhNmEgg6U58d6ixt8pbV8lVM2E/k1Ms9AvRHA/JsA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L4mGs4P2foMzToS3dTnp8/3ihHX8xu9NkFMtrxbud5a8Ez1+JNmtbuv4z8QVjJ3aHjHaKL+h2wCOBYFf1vE/y+NBhvkQKq7kiCpmzZTBqsVcUIFrBm8cHTtOdXXMjAhdexCWzhKfsRODuV3t7SsNUXKeF29CkkysH85M6ADzCuE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.188 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4ZJvNf4TspzCs7l; Fri, 21 Mar 2025 15:34:58 +0800 (CST) Received: from kwepemd200014.china.huawei.com (unknown [7.221.188.8]) by mail.maildlp.com (Postfix) with ESMTPS id 56367140159; Fri, 21 Mar 2025 15:38:35 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by kwepemd200014.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 21 Mar 2025 15:38:34 +0800 From: Yicong Yang To: , , , CC: , , , , , , Jonathan Cameron Subject: [PATCH v2 6/8] drivers/perf: hisi: Support PMUs with no interrupt Date: Fri, 21 Mar 2025 15:38:44 +0800 Message-ID: <20250321073846.23507-7-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20250321073846.23507-1-yangyicong@huawei.com> References: <20250321073846.23507-1-yangyicong@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd200014.china.huawei.com (7.221.188.8) Content-Type: text/plain; charset="utf-8" From: Yicong Yang We'll have PMUs don't have an interrupt to indicate the counter overflow, but the Uncore PMU core assume all the PMUs have interrupt. So handle this case in the core. The existing PMUs won't be affected. Reviewed-by: Jonathan Cameron Signed-off-by: Yicong Yang --- drivers/perf/hisilicon/hisi_uncore_pmu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisili= con/hisi_uncore_pmu.c index ef058b1dd509..a449651f79c9 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -510,7 +510,9 @@ int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct= hlist_node *node) return 0; =20 hisi_pmu->on_cpu =3D cpumask_local_spread(0, dev_to_node(hisi_pmu->dev)); - WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(hisi_pmu->on_cpu))); + if (hisi_pmu->irq > 0) + WARN_ON(irq_set_affinity(hisi_pmu->irq, + cpumask_of(hisi_pmu->on_cpu))); return 0; } =20 @@ -525,7 +527,8 @@ int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct= hlist_node *node) hisi_pmu->on_cpu =3D cpu; =20 /* Overflow interrupt also should use the same CPU */ - WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu))); + if (hisi_pmu->irq > 0) + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu))); =20 return 0; } @@ -560,7 +563,9 @@ int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struc= t hlist_node *node) perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target); /* Use this CPU for event counting */ hisi_pmu->on_cpu =3D target; - WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target))); + + if (hisi_pmu->irq > 0) + WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target))); =20 return 0; } --=20 2.24.0