From nobody Mon Feb 9 23:00:50 2026 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1DB241EEA3D for ; Fri, 21 Mar 2025 07:38:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742542718; cv=none; b=uZ8hh6aCfLI/M1Mv7X04v7pOpeXuLkkOza7Fl3fku3XJYeVuGKw8mlvSeIVd8hQeeY1T9xICwHQojBKtQQrMkQ0bxHaIZYfOqjETd3Ea/IWCrhXyoACFtOKoPvlvhl2IribJ9fjnaGqF4V71SqIExVLSznGQxtc+KpMfYlw7+FY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742542718; c=relaxed/simple; bh=uoLgiES/dfx8er3hrl4HglCoF+f3qY2anNwqB7c8KoA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ImEvMfQAI86X4aVq4l+Y7zYNj1mnCb6pk1y+RBUhqmv5qneLooomirPzpXevmbfimB1lw/cq1fOL2QGgecJYpa4CK9aY0IPU3OoIn53vSWxJjUpsDWcu5VedvYGVjIgBkdAAz9o4h2LWbxHdBbvYzPlyXxMPc2R8Wz7IE6Z955s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4ZJvST4GKXz13L0s; Fri, 21 Mar 2025 15:38:17 +0800 (CST) Received: from kwepemd200014.china.huawei.com (unknown [7.221.188.8]) by mail.maildlp.com (Postfix) with ESMTPS id ABBD9140159; Fri, 21 Mar 2025 15:38:33 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by kwepemd200014.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 21 Mar 2025 15:38:33 +0800 From: Yicong Yang To: , , , CC: , , , , , , Jonathan Cameron Subject: [PATCH v2 2/8] drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver Date: Fri, 21 Mar 2025 15:38:40 +0800 Message-ID: <20250321073846.23507-3-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20250321073846.23507-1-yangyicong@huawei.com> References: <20250321073846.23507-1-yangyicong@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To kwepemd200014.china.huawei.com (7.221.188.8) Content-Type: text/plain; charset="utf-8" From: Junhao He HiSilicon DDRC v3 PMU has the different interrupt register offset compared to the v2. Add device information of v3 PMU with ACPI HID HISI0235. Signed-off-by: Junhao He Reviewed-by: Jonathan Cameron Signed-off-by: Yicong Yang --- drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c b/drivers/perf/h= isilicon/hisi_uncore_ddrc_pmu.c index 7e3c2436e96b..26eaa6d20c00 100644 --- a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c @@ -43,6 +43,11 @@ #define DDRC_V2_EVENT_TYPE 0xe74 #define DDRC_V2_PERF_CTRL 0xeA0 =20 +/* DDRC interrupt registers definition in v3 */ +#define DDRC_V3_INT_MASK 0x534 +#define DDRC_V3_INT_STATUS 0x538 +#define DDRC_V3_INT_CLEAR 0x53C + /* DDRC has 8-counters */ #define DDRC_NR_COUNTERS 0x8 #define DDRC_V1_PERF_CTRL_EN 0x2 @@ -460,9 +465,28 @@ static const struct hisi_pmu_dev_info hisi_ddrc_v2 =3D= { .private =3D &hisi_ddrc_v2_pmu_regs, }; =20 +static struct hisi_ddrc_pmu_regs hisi_ddrc_v3_pmu_regs =3D { + .event_cnt =3D DDRC_V2_EVENT_CNT, + .event_ctrl =3D DDRC_V2_EVENT_CTRL, + .event_type =3D DDRC_V2_EVENT_TYPE, + .perf_ctrl =3D DDRC_V2_PERF_CTRL, + .perf_ctrl_en =3D DDRC_V2_PERF_CTRL_EN, + .int_mask =3D DDRC_V3_INT_MASK, + .int_clear =3D DDRC_V3_INT_CLEAR, + .int_status =3D DDRC_V3_INT_STATUS, +}; + +static const struct hisi_pmu_dev_info hisi_ddrc_v3 =3D { + .counter_bits =3D 48, + .check_event =3D DDRC_V2_NR_EVENTS, + .attr_groups =3D hisi_ddrc_pmu_v2_attr_groups, + .private =3D &hisi_ddrc_v3_pmu_regs, +}; + static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] =3D { { "HISI0233", (kernel_ulong_t)&hisi_ddrc_v1 }, { "HISI0234", (kernel_ulong_t)&hisi_ddrc_v2 }, + { "HISI0235", (kernel_ulong_t)&hisi_ddrc_v3 }, {} }; MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match); --=20 2.24.0