From nobody Wed Dec 17 10:44:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BA551E98EF; Fri, 21 Mar 2025 02:29:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742524160; cv=none; b=RNtIyMzPbpbuG+88cw+SNvXKtZcVkGwvOTJw2Ybe6y2jMbE3zssx0qDp2pdiwq4OefwgHwhkqE0s8aadR3P6z3GsTenELAEI05cLcGkPJ+S37vZbuEMPeKqf6b017fJQ66KITIzPJrVdlYXfs/sAs7BiZvSKMIDLMj0zjstkDG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742524160; c=relaxed/simple; bh=Ovxkur7Th1bj1n91ym6geZ1kTrWIxYLfjpr2pVhZrw4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=naBIFMhPlMNwKW0/+ZArzBcIR+kdVHZH9mSgv5Hd9SwsW5AqIb6UnaS8AIYBjrYxI5A4tlfGFjyku10ghDH6kRNmZ+NhU6p6+itdA0rtjJOs5xeEsG373n23vSbtH3XUnOLUEcvt70D5+GWGgdIml4XFUkpU7mew3QfmYtssbg8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pxh4gFTy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pxh4gFTy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B2FC0C4CEF7; Fri, 21 Mar 2025 02:29:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742524160; bh=Ovxkur7Th1bj1n91ym6geZ1kTrWIxYLfjpr2pVhZrw4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pxh4gFTy0ybOH1FBbRwoZIVC8/faPSWiTXVqtlECiovY8e1kEXNTIcE0KWSLrZjH8 FAdbYCZwiOCb2TJFrfA9dvipZD2v60WdywejqzQtJZEDKxqGCSkWfNn9ojjqngvgVQ qFJoQSbL7OFNXStTWlNS6xQvXcFmBcCIipqWN6vRND2zM8SBZFBESlvX4iXIfWlM3y 9KjEKdAD8w6mE0dhJdQ6HAi0n0xt1Defx3UGpHsgMqaW35tABKmckPEPIUaIjQcBfE DpgZoGX2F4Y9p5QH0LvRm29Ng3ty2fbV5ugQJCf9kOEx/x4jluIolRyfjnyqsq/NBb zEjJDXnfd+dWw== From: Mario Limonciello To: "Gautham R . Shenoy" , Perry Yuan Cc: Dhananjay Ugwekar , linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), linux-pm@vger.kernel.org (open list:CPU FREQUENCY SCALING FRAMEWORK), Mario Limonciello Subject: [PATCH v4 5/5] cpufreq/amd-pstate-ut: Add a unit test for raw EPP Date: Thu, 20 Mar 2025 21:28:58 -0500 Message-ID: <20250321022858.1538173-6-superm1@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250321022858.1538173-1-superm1@kernel.org> References: <20250321022858.1538173-1-superm1@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mario Limonciello Ensure that all supported raw EPP values work properly. Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate-ut.c | 58 +++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-u= t.c index e671bc7d15508..d0c5c0aa3cc94 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include =20 @@ -33,6 +34,7 @@ =20 #include "amd-pstate.h" =20 +DEFINE_FREE(free_page, void *, if (_T) free_page((unsigned long)_T)) =20 struct amd_pstate_ut_struct { const char *name; @@ -46,6 +48,7 @@ static int amd_pstate_ut_acpi_cpc_valid(u32 index); static int amd_pstate_ut_check_enabled(u32 index); static int amd_pstate_ut_check_perf(u32 index); static int amd_pstate_ut_check_freq(u32 index); +static int amd_pstate_ut_epp(u32 index); static int amd_pstate_ut_check_driver(u32 index); =20 static struct amd_pstate_ut_struct amd_pstate_ut_cases[] =3D { @@ -53,6 +56,7 @@ static struct amd_pstate_ut_struct amd_pstate_ut_cases[] = =3D { {"amd_pstate_ut_check_enabled", amd_pstate_ut_check_enabled }, {"amd_pstate_ut_check_perf", amd_pstate_ut_check_perf }, {"amd_pstate_ut_check_freq", amd_pstate_ut_check_freq }, + {"amd_pstate_ut_epp", amd_pstate_ut_epp }, {"amd_pstate_ut_check_driver", amd_pstate_ut_check_driver } }; =20 @@ -239,6 +243,60 @@ static int amd_pstate_set_mode(enum amd_pstate_mode mo= de) return amd_pstate_update_status(mode_str, strlen(mode_str)); } =20 +static int amd_pstate_ut_epp(u32 index) +{ + struct cpufreq_policy *policy __free(put_cpufreq_policy) =3D NULL; + void *buf __free(free_page) =3D NULL; + struct amd_cpudata *cpudata; + int ret, cpu =3D 0; + u16 epp; + + policy =3D cpufreq_cpu_get(cpu); + if (!policy) + return -ENODEV; + + cpudata =3D policy->driver_data; + + /* disable dynamic EPP before running test */ + if (cpudata->dynamic_epp) { + pr_debug("Dynamic EPP is enabled, disabling it\n"); + amd_pstate_clear_dynamic_epp(policy); + } + + buf =3D (void *)__get_free_page(GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret =3D amd_pstate_set_mode(AMD_PSTATE_ACTIVE); + if (ret) + return ret; + + for (epp =3D 0; epp <=3D U8_MAX; epp++) { + u8 val; + + /* write all EPP values */ + memset(buf, 0, sizeof(*buf)); + snprintf(buf, PAGE_SIZE, "%d", epp); + ret =3D store_energy_performance_preference(policy, buf, sizeof(*buf)); + if (ret < 0) + return ret; + + /* check if the EPP value reads back correctly for raw numbers */ + memset(buf, 0, sizeof(*buf)); + ret =3D show_energy_performance_preference(policy, buf); + if (ret < 0) + return ret; + strreplace(buf, '\n', '\0'); + ret =3D kstrtou8(buf, 0, &val); + if (!ret && epp !=3D val) { + pr_err("Raw EPP value mismatch: %d !=3D %d\n", epp, val); + return -EINVAL; + } + } + + return 0; +} + static int amd_pstate_ut_check_driver(u32 index) { enum amd_pstate_mode mode1, mode2 =3D AMD_PSTATE_DISABLE; --=20 2.43.0