From nobody Mon Feb 9 18:01:27 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E10322FE02; Fri, 21 Mar 2025 17:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742577811; cv=none; b=GZKSjcntM83v2vec99GcDW6s+yY/e5uuBUzDk/7vdtfDA6VJC9LdH5hm73Qi0c4K/AscDfIRs2DrfBJy/a3YJat1Mtds0JgweHOqX51VnWOdwGonLac6JpkjhdsKwD5FU7X2fqgW8QTXShROJca+j93wfjnJ4fNwEIgEKmaRL34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742577811; c=relaxed/simple; bh=NRPZVMg8q8Glkkek+MZ6GcEzInHhK6SX1BhDs6BGtW4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kC4IONeKCBhugMpVHpWIlJuRMA8cP8IRLr/JygVRf+aPQqpTwfs1ADx4xRihh5qb8Z/aT/1m6ktMLurSjer20d9gtITMl87KBmPAzWqnuBYjxYV880WF16qcv7NWWc6D/GDwTt3ROBrICcaB0UwpUC3GGnjvEReBjviqxA8OjFI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mo0eTwd4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mo0eTwd4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 72855C4CEE8; Fri, 21 Mar 2025 17:23:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1742577810; bh=NRPZVMg8q8Glkkek+MZ6GcEzInHhK6SX1BhDs6BGtW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mo0eTwd46VQIln6hxjk3OQXTODpg3IEBL3QgxORx7opDBGbPqm3zC6Tb3yZAnFUg/ ZfpHYuSCjNlR/W/PK9ES7Ynnp/fwBiD876cWYfGvFV8z+wz0pSjQLZrmskSN8zl8nu SGkrln0yZmXOtbMigQ1XaPHtnJ9lu3DMf5iOsnilfEIupaiALC7p6GfmwHuCiY4/VV jOrn/icFy1wII4u601qNyFYII4LpKDB0B6jQvmMEYxyV8Q6pPWYB5tAIZDn4nWAuq+ xNvTtgEyb5E8w7Bjx3I1sMSwH1U8lM/HQr7VBcq51yMidT0Lt+XasT+1z5cbkHc5Wr 7FNOFHo/EvjpQ== From: Conor Dooley To: Stephen Boyd Cc: conor@kernel.org, Conor Dooley , Daire McNamara , pierre-henry.moussay@microchip.com, valentina.fernandezalanis@microchip.com, Michael Turquette , Rob Herring , Krzysztof Kozlowski , Jassi Brar , Lee Jones , Paul Walmsley , Palmer Dabbelt , Philipp Zabel , linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 5/9] dt-bindings: clk: microchip: mpfs: remove first reg region Date: Fri, 21 Mar 2025 17:22:38 +0000 Message-ID: <20250321-majesty-overhung-1441f3858efc@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250321-cuddly-hazily-d0ab1e1747b5@spud> References: <20250321-cuddly-hazily-d0ab1e1747b5@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3159; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=PXlK/3bLOMNEyxgWeBhvy5NgnPZBRf51ELypfcFIriA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOl3F0TN8Nev1tRQ3O5wNHDiGTafNYdszRYKFQkzbSqa7 86i/bamo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABMxnsbIcGvGSY3l/1sn205d XNi/J3Vbt0qJefYOuV1tSrn/ZsT/NmH4pxWYLs7NPm9FRlOFnPfyV3Ilm5SSbM9Lf5/lfO+F1oG 9TAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The first reg region in this binding is not exclusively for clocks, as evidenced by the dual role of this device as a reset controller at present. The first region is however better described by a simple-mfd syscon, but this would have require a significant re-write of the devicetree for the platform, so the easy way out was chosen when reset support was first introduced. The region doesn't just contain clock and reset registers, it also contains pinctrl and interrupt controller functionality, so drop the region from the clock binding so that it can be described instead by a simple-mfd syscon rather than propagate this incorrect description of the hardware to the new pic64gx SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- .../bindings/clock/microchip,mpfs-clkcfg.yaml | 36 +++++++++++-------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.= yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index e4e1c31267d2..ee4f31596d97 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -22,16 +22,23 @@ properties: const: microchip,mpfs-clkcfg =20 reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, = cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and r= eset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of th= e mss - pll + oneOf: + - items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for t= he, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable a= nd reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll + deprecated: true + - items: + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration o= f the mss + pll =20 clocks: maxItems: 1 @@ -69,11 +76,12 @@ examples: - | #include soc { - #address-cells =3D <2>; - #size-cells =3D <2>; - clkcfg: clock-controller@20002000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + + clkcfg: clock-controller@3E001000 { compatible =3D "microchip,mpfs-clkcfg"; - reg =3D <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0= x1000>; + reg =3D <0x3E001000 0x1000>; clocks =3D <&ref>; #clock-cells =3D <1>; }; --=20 2.45.2